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author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2013-11-29 13:31:25 (GMT) |
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committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-14 05:43:34 (GMT) |
commit | 96a2859e54c8f6153ddb429ba730b324ab8ff352 (patch) | |
tree | 8890a8ad20c02a1bdfade488cadc48b8147224a6 /arch/arm/include/asm/arch-zynq | |
parent | 5b73caffeb12b0f635693ce4c53177de86dd3b38 (diff) | |
download | u-boot-fsl-qoriq-96a2859e54c8f6153ddb429ba730b324ab8ff352.tar.xz |
ARM: zynq: Added efuse status register base address
Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include/asm/arch-zynq')
-rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 39184da..20f62bf 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -22,6 +22,7 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0xF @@ -130,4 +131,12 @@ struct ddrc_regs { }; #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a68e1b3..2445a04 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -16,6 +16,7 @@ extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); |