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author | Michal Simek <michal.simek@xilinx.com> | 2013-04-22 13:43:02 (GMT) |
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committer | Michal Simek <michal.simek@xilinx.com> | 2013-05-06 08:41:24 (GMT) |
commit | d5dae85f23c7c902731512e451afde9a6e4a250a (patch) | |
tree | 8b7230045d9b0c43400e2ed661fb9282c662472c /arch/arm/include/asm/arch-zynq | |
parent | 5bd0bd7cef396a830996b4ad91b89b7d205c7298 (diff) | |
download | u-boot-fsl-qoriq-d5dae85f23c7c902731512e451afde9a6e4a250a.tar.xz |
fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-zynq')
-rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 3 |
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 6af892a..8b8a91a 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -53,11 +53,17 @@ struct slcr_regs { u32 boot_mode; /* 0x25c */ u32 reserved4[116]; u32 trust_zone; /* 0x430 */ /* FIXME */ - u32 reserved5[115]; + u32 reserved5_1[63]; + u32 pss_idcode; /* 0x530 */ + u32 reserved5_2[51]; u32 ddr_urgent; /* 0x600 */ u32 reserved6[6]; u32 ddr_urgent_sel; /* 0x61c */ - u32 reserved7[188]; + u32 reserved7[56]; + u32 mio_pin[54]; /* 0x700 - 0x7D4 */ + u32 reserved8[74]; + u32 lvl_shftr_en; /* 0x900 */ + u32 reserved9[3]; u32 ocm_cfg; /* 0x910 */ }; diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index af9e7f8..2317121 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -27,6 +27,9 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); +extern void zynq_slcr_devcfg_disable(void); +extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_idcode(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); |