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| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 09:52:14 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-15 12:46:43 (GMT) |
| commit | ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 (patch) | |
| tree | 0e6da861d32909eb34dce4f2c20d30d803d0f2ea /arch/arm/include/asm/armv8 | |
| parent | 55aa0bed9803b8a5bd3e462fd712741c2e1cff1b (diff) | |
| download | u-boot-fsl-qoriq-ad3d6e88a1a4e6aacc55b39c2bad1528100784c0.tar.xz | |
armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/armv8')
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index a1c3c06..587ee39 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -110,6 +110,10 @@ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#define TCR_EL1_RSVD (1 << 31) +#define TCR_EL2_RSVD (1 << 31 | 1 << 23) +#define TCR_EL3_RSVD (1 << 31 | 1 << 23) + #ifndef __ASSEMBLY__ void set_pgtable_section(u64 *page_table, u64 index, |