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authorSjoerd Simons <sjoerd.simons@collabora.co.uk>2016-02-28 21:24:59 (GMT)
committerSimon Glass <sjg@chromium.org>2016-05-27 15:00:48 (GMT)
commit0aefc0b0c7eba963c88eca893a546f3e786615ac (patch)
treea04f3c181e74d338b8fec3d99656f8eb0dd250bd /arch/arm/include/asm
parent70f7a2cdac6a7f75f27848d689a13ca244b0792b (diff)
downloadu-boot-fsl-qoriq-0aefc0b0c7eba963c88eca893a546f3e786615ac.tar.xz
rockchip: rk3288: Add clock support for the gmac ethernet interface
Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3288.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d2690c7..8a8ca9c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@ enum {
SDIO0_DIV_MASK = 0x3f,
};
+/* CRU_CLKSEL21_CON */
+enum {
+ MAC_DIV_CON_SHIFT = 0xf,
+ MAC_DIV_CON_MASK = 0x1f,
+
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK = 1,
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+ EMAC_PLL_SHIFT = 0,
+ EMAC_PLL_MASK = 0x3,
+ EMAC_PLL_SELECT_NEW = 0x0,
+ EMAC_PLL_SELECT_CODEC = 0x1,
+ EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,