diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2015-08-10 11:22:55 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-28 16:33:19 (GMT) |
| commit | 7beaf8b6903f2ef4ab8d1d36ee4b0ea4e8611ffd (patch) | |
| tree | 9c0b7d780e70fb5b7f4a283033c1f51f01d39d60 /arch/arm/include/asm | |
| parent | 8af1be7678c1fd9bc03b28f0756c586fb3d47d29 (diff) | |
| download | u-boot-fsl-qoriq-7beaf8b6903f2ef4ab8d1d36ee4b0ea4e8611ffd.tar.xz | |
ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/omap_common.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f8e5630..38d50d6 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -172,6 +172,9 @@ /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) +/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ +#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) + /* CM_L3INIT_USB_OTG_SS_CLKCTRL */ #define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) #define OPTFCLKEN_REFCLK960M (1 << 8) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2461667..37117e2 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -145,6 +145,7 @@ struct prcm_regs { u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; + u32 cm_coreaon_l3init_60m_gfclk_clkctrl; /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; @@ -231,6 +232,7 @@ struct prcm_regs { u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; u32 cm_l3init_usb_otg_ss1_clkctrl; + u32 cm_l3init_usb_otg_ss2_clkctrl; u32 prm_irqstatus_mpu_2; |