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authorPeng Fan <peng.fan@nxp.com>2017-02-22 08:21:51 (GMT)
committerStefano Babic <sbabic@denx.de>2017-03-17 08:27:08 (GMT)
commitc40d612b1a6e1c63f27089d1d8fa3016164cacdb (patch)
tree40ca0a2e0d0251238aa36340754a3c12a9214000 /arch/arm/include
parent7ee3f149fe776d3e46dbb517bf04ee29ec075709 (diff)
downloadu-boot-fsl-qoriq-c40d612b1a6e1c63f27089d1d8fa3016164cacdb.tar.xz
serial: lpuart: restructure lpuart driver
Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h42
-rw-r--r--arch/arm/include/asm/arch-ls102xa/imx-regs.h40
-rw-r--r--arch/arm/include/asm/arch-vf610/clock.h1
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h28
4 files changed, 1 insertions, 110 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
index 57e417b..b0e58ca 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -10,46 +10,4 @@
#define I2C_QUIRK_REG /* enable 8-bit driver */
-#ifdef CONFIG_FSL_LPUART
-#ifdef CONFIG_LPUART_32B_REG
-struct lpuart_fsl {
- u32 baud;
- u32 stat;
- u32 ctrl;
- u32 data;
- u32 match;
- u32 modir;
- u32 fifo;
- u32 water;
-};
-#else
-struct lpuart_fsl {
- u8 ubdh;
- u8 ubdl;
- u8 uc1;
- u8 uc2;
- u8 us1;
- u8 us2;
- u8 uc3;
- u8 ud;
- u8 uma1;
- u8 uma2;
- u8 uc4;
- u8 uc5;
- u8 ued;
- u8 umodem;
- u8 uir;
- u8 reserved;
- u8 upfifo;
- u8 ucfifo;
- u8 usfifo;
- u8 utwfifo;
- u8 utcfifo;
- u8 urwfifo;
- u8 urcfifo;
- u8 rsvd[28];
-};
-#endif
-#endif /* CONFIG_FSL_LPUART */
-
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
index f9cd75b..7190f3d 100644
--- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h
+++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
@@ -10,44 +10,4 @@
#define I2C_QUIRK_REG /* enable 8-bit driver */
-#ifdef CONFIG_LPUART_32B_REG
-struct lpuart_fsl {
- u32 baud;
- u32 stat;
- u32 ctrl;
- u32 data;
- u32 match;
- u32 modir;
- u32 fifo;
- u32 water;
-};
-#else
-struct lpuart_fsl {
- u8 ubdh;
- u8 ubdl;
- u8 uc1;
- u8 uc2;
- u8 us1;
- u8 us2;
- u8 uc3;
- u8 ud;
- u8 uma1;
- u8 uma2;
- u8 uc4;
- u8 uc5;
- u8 ued;
- u8 umodem;
- u8 uir;
- u8 reserved;
- u8 upfifo;
- u8 ucfifo;
- u8 usfifo;
- u8 utwfifo;
- u8 utcfifo;
- u8 urwfifo;
- u8 urcfifo;
- u8 rsvd[28];
-};
-#endif
-
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index e5a5c6d..c5ba240 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,7 @@ enum mxc_clock {
void enable_ocotp_clk(unsigned char enable);
unsigned int mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 9758323..cac68ef 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -429,34 +429,6 @@ struct fuse_bank4_regs {
u32 rsvd7[3];
};
-/* UART */
-struct lpuart_fsl {
- u8 ubdh;
- u8 ubdl;
- u8 uc1;
- u8 uc2;
- u8 us1;
- u8 us2;
- u8 uc3;
- u8 ud;
- u8 uma1;
- u8 uma2;
- u8 uc4;
- u8 uc5;
- u8 ued;
- u8 umodem;
- u8 uir;
- u8 reserved;
- u8 upfifo;
- u8 ucfifo;
- u8 usfifo;
- u8 utwfifo;
- u8 utcfifo;
- u8 urwfifo;
- u8 urcfifo;
- u8 rsvd[28];
-};
-
/* MSCM Interrupt Router */
struct mscm_ir {
u32 ircp0ir;