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| author | Hans de Goede <hdegoede@redhat.com> | 2015-11-20 18:29:49 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-12-10 10:14:16 (GMT) |
| commit | cbc1a91afb7fb0f096453e5574bc5c0719c6c9c4 (patch) | |
| tree | 9fb14aefe0f3eb502d335f4183b6eb65a71c17b0 /arch/arm/include | |
| parent | 789fa275b3750e60c60cb3d18eabc9467892c257 (diff) | |
| download | u-boot-fsl-qoriq-cbc1a91afb7fb0f096453e5574bc5c0719c6c9c4.tar.xz | |
sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 09337a1..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -220,11 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) -#if defined CONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ -#endif #define AXI_GATE_OFFSET_DRAM 0 |