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author | Nishanth Menon <nm@ti.com> | 2016-03-23 15:14:19 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-04-01 21:17:40 (GMT) |
commit | 2283284b05326bf1384873f2a59b77fe0d9b2f8f (patch) | |
tree | de8dee4a8c1c0475b6c61e920fbb7a14eb0f781d /arch/arm/mach-keystone/init.c | |
parent | 1f807a9f32aaa4e4917336912fd867671954d18c (diff) | |
download | u-boot-fsl-qoriq-2283284b05326bf1384873f2a59b77fe0d9b2f8f.tar.xz |
ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------
0 | C66x 0 | C66x 0 | C66x 0 | C66x 0
1 | C66x 1 | C66x 1 | Reserved | ARM
2 | C66x 2 | C66x 2 | Reserved | ICSS0
3 | C66x 3 | C66x 3 | Reserved | ICSS1
4 | C66x 4 | Reserved | Reserved | NETCP
5 | C66x 5 | Reserved | Reserved | CPIE
6 | C66x 6 | Reserved | Reserved | USB
7 | C66x 7 | Reserved | Reserved | Reserved
8 | ARM | ARM | ARM | MLB
9 | NetCP | NetCP | NetCP | PMMC
10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS
11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC
12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13 | Reserved | Reserved | PCIe_1 | Reserved
14 | HyperLink | PCIe_1 | HyperLink | Reserved
15 | Reserved | Reserved | TSIP | Reserved
-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).
By marking these segments as shared, we also ensure SoC wide coherency
is enabled.
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-keystone/init.c')
-rw-r--r-- | arch/arm/mach-keystone/init.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 2368315..3b6d5ef 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -98,29 +98,57 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode) static void msmc_k2hkle_common_setup(void) { + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); #ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); #endif msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); + msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); +} + +static void msmc_k2hk_setup(void) +{ + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7); + msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK); } static inline void msmc_k2l_setup(void) { + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2); + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3); msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1); } static inline void msmc_k2e_setup(void) { msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1); + msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK); + msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP); } -static inline void msmc_k2g_setup(void) +static void msmc_k2g_setup(void) { + msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM); + msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0); + msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1); msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS); msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE); + msmc_share_all_segments(K2G_MSMC_SEGMENT_USB); + msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB); + msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC); + msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS); + msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC); + msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); } int arch_cpu_init(void) @@ -136,6 +164,8 @@ int arch_cpu_init(void) msmc_k2e_setup(); else if (cpu_is_k2l()) msmc_k2l_setup(); + else + msmc_k2hk_setup(); } /* Initialize the PCIe-0 to work as Root Complex */ |