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| author | Cooper Jr., Franklin <fcooper@ti.com> | 2017-06-16 22:25:21 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-07-10 18:25:57 (GMT) |
| commit | e5e546aad18a725787e6c6b6aa1383b02eed0723 (patch) | |
| tree | e6ec3a19bdb5e70439a7256686de0a65541c269b /arch/arm/mach-keystone | |
| parent | a76a6f3e0434b68de30fbdf2825dea8060d066fd (diff) | |
| download | u-boot-fsl-qoriq-e5e546aad18a725787e6c6b6aa1383b02eed0723.tar.xz | |
ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-keystone')
| -rw-r--r-- | arch/arm/mach-keystone/ddr3.c | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 25a9637..4cad6a2 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -65,11 +65,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; if (cpu_is_k2g()) { - setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); + clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET, + phy_cfg->datx8_2_mask, + phy_cfg->datx8_2_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET, + phy_cfg->datx8_3_mask, + phy_cfg->datx8_3_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, + phy_cfg->datx8_4_mask, + phy_cfg->datx8_4_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, + phy_cfg->datx8_5_mask, + phy_cfg->datx8_5_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, + phy_cfg->datx8_6_mask, + phy_cfg->datx8_6_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, + phy_cfg->datx8_7_mask, + phy_cfg->datx8_7_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, + phy_cfg->datx8_8_mask, + phy_cfg->datx8_8_val); } __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); |