diff options
author | huang lin <hl@rock-chips.com> | 2015-11-17 06:20:09 (GMT) |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2015-12-01 15:07:22 (GMT) |
commit | cc2244b8fa85b4a8af228617ed7566785dfb1728 (patch) | |
tree | a688f3f3f8b7301053262f64270bfc76f98df769 /arch/arm/mach-rockchip/rk_timer.c | |
parent | abe919ec5487bda93245369eb103b20e182fd8b5 (diff) | |
download | u-boot-fsl-qoriq-cc2244b8fa85b4a8af228617ed7566785dfb1728.tar.xz |
rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-rockchip/rk_timer.c')
-rw-r--r-- | arch/arm/mach-rockchip/rk_timer.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c new file mode 100644 index 0000000..ae5123d --- /dev/null +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/timer.h> +#include <asm/io.h> +#include <common.h> +#include <linux/types.h> + +struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; + +static uint64_t rockchip_get_ticks(void) +{ + uint64_t timebase_h, timebase_l; + + timebase_l = readl(&timer_ptr->timer_curr_value0); + timebase_h = readl(&timer_ptr->timer_curr_value1); + + return timebase_h << 32 | timebase_l; +} + +static uint64_t usec_to_tick(unsigned int usec) +{ + uint64_t tick = usec; + tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000); + return tick; +} + +void rockchip_udelay(unsigned int usec) +{ + uint64_t tmp; + + /* get timestamp */ + tmp = rockchip_get_ticks() + usec_to_tick(usec); + + /* loop till event */ + while (rockchip_get_ticks() < tmp+1) + ; +} + +void rockchip_timer_init(void) +{ + writel(0xffffffff, &timer_ptr->timer_load_count0); + writel(0xffffffff, &timer_ptr->timer_load_count1); + writel(1, &timer_ptr->timer_ctrl_reg); +} |