ARM: uniphier: remove SPL support for ARMv8 SoCs

It has been a while since ARM Trusted Firmware supported UniPhier SoC
family.  U-Boot SPL was intended as a temporary loader that runs in
secure world.  It is a maintenance headache to support two different
boot mechanisms.  Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

5 files changed, 0 insertions, 139 deletions

diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile
index 06072f2..12d91e0 100644
--- a/arch/arm/mach-uniphier/arm64/Makefile
+++ b/arch/arm/mach-uniphier/arm64/Makefile
@@ -2,14 +2,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifdef CONFIG_SPL_BUILD
-obj-y += timer.o
-else
 obj-y += mem_map.o
-ifdef CONFIG_ARMV8_MULTIENTRY
-obj-y += smp.o smp_kick_cpus.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
-else
 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o
-endif
-endif
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
deleted file mode 100644
index bf0fad4..0000000
--- a/arch/arm/mach-uniphier/arm64/arm-cci500.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
- *
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-
-#define CCI500_BASE			0x5FD00000
-#define CCI500_SLAVE_OFFSET		0x1000
-
-#define CCI500_SNOOP_CTRL
-#define   CCI500_SNOOP_CTRL_EN_DVM	BIT(1)
-#define   CCI500_SNOOP_CTRL_EN_SNOOP	BIT(0)
-
-void cci500_init(unsigned int nr_slaves)
-{
-	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
-	int i;
-
-	for (i = 0; i < nr_slaves; i++) {
-		void __iomem *base;
-		u32 tmp;
-
-		base = ioremap(slave_base, SZ_4K);
-
-		tmp = readl(base);
-		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
-		writel(tmp, base);
-
-		iounmap(base);
-
-		slave_base += CCI500_SLAVE_OFFSET;
-	}
-}
diff --git a/arch/arm/mach-uniphier/arm64/smp.S b/arch/arm/mach-uniphier/arm64/smp.S
deleted file mode 100644
index 9348ec9..0000000
--- a/arch/arm/mach-uniphier/arm64/smp.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-ENTRY(uniphier_smp_setup)
-	mrs	x0, s3_1_c15_c2_1	/* CPUECTLR_EL1 */
-	orr	x0, x0, #(1 << 6)	/* SMPEN */
-	msr	s3_1_c15_c2_1, x0
-	ret
-ENDPROC(uniphier_smp_setup)
-
-ENTRY(uniphier_secondary_startup)
-	bl	uniphier_smp_setup
-	b	_start
-ENDPROC(uniphier_secondary_startup)
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
deleted file mode 100644
index 8e5b198..0000000
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-
-#define UNIPHIER_SMPCTRL_ROM_RSV0	0x59801200
-
-void uniphier_smp_setup(void);
-void uniphier_secondary_startup(void);
-
-void uniphier_smp_kick_all_cpus(void)
-{
-	void __iomem *rom_boot_rsv0;
-
-	rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
-
-	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
-
-	iounmap(rom_boot_rsv0);
-
-	uniphier_smp_setup();
-
-	asm("dsb	ishst\n" /* Ensure the write to ROM_RSV0 is visible */
-	    "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
-}
diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c
deleted file mode 100644
index c10903a..0000000
--- a/arch/arm/mach-uniphier/arm64/timer.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#define CNT_CONTROL_BASE	0x60E00000
-
-#define CNTCR			0x000
-#define   CNTCR_EN			BIT(0)
-
-/* setup ARMv8 Generic Timer */
-int timer_init(void)
-{
-	void __iomem *base;
-	u32 tmp;
-
-	base = ioremap(CNT_CONTROL_BASE, SZ_4K);
-
-	/*
-	 * Note:
-	 * In a system that implements both Secure and Non-secure states,
-	 * this register is only writable in Secure state.
-	 */
-	tmp = readl(base + CNTCR);
-	tmp |= CNTCR_EN;
-	writel(tmp, base + CNTCR);
-
-	iounmap(base);
-
-	return 0;
-}