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| author | Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> | 2017-01-17 15:27:24 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-02-17 09:22:46 (GMT) |
| commit | a259243e9d5895e03348cad98b82524e61cd47e8 (patch) | |
| tree | 56186173d41941656bd4e0339e166cb5d72efc65 /arch/arm/mach-zynq | |
| parent | 85d0bea153c76f4a3912b5683222885bfd37c769 (diff) | |
| download | u-boot-fsl-qoriq-a259243e9d5895e03348cad98b82524e61cd47e8.tar.xz | |
net: zynq: Don't overwrite gem_rclk_ctrl with default value
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq')
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 2d3bf2a..c1129cd 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -140,13 +140,6 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) if (ret) goto out; - if (gem_id) { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem1_rclk_ctrl); - } else { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem0_rclk_ctrl); - } udelay(100000); out: zynq_slcr_lock(); |