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| author | Tom Warren <twarren@nvidia.com> | 2013-03-28 17:03:22 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 18:01:37 (GMT) |
| commit | 3ebbbfe4c78089db47599fc7b57ad016e247dd52 (patch) | |
| tree | 3bc360d6283b765296322ae70e0eae6d84660015 /arch/arm | |
| parent | 3efff99fbd971cd087569162e8f00f8f91cd3f22 (diff) | |
| download | u-boot-fsl-qoriq-3ebbbfe4c78089db47599fc7b57ad016e247dd52.tar.xz | |
Tegra: Restore cp15 VBAR _start vector write for ARMv7
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5feae7a..e9e57e6 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -253,11 +253,9 @@ ENTRY(c_runtime_cpu_setup) /* * Move vector table */ -#if !defined(CONFIG_TEGRA) /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR -#endif /* !Tegra */ bx lr |