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| author | Michal Simek <michal.simek@xilinx.com> | 2014-03-27 09:06:43 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-14 05:43:34 (GMT) |
| commit | 6e04769caf208a9f2da8ef8a85353def2a170176 (patch) | |
| tree | 59612568d3a1cb8ebed5cddee1ad079684fb1031 /arch/arm | |
| parent | 1540fb725bb7067f5cacbcc624f8684ed1471815 (diff) | |
| download | u-boot-fsl-qoriq-6e04769caf208a9f2da8ef8a85353def2a170176.tar.xz | |
ARM: zynq: slcr: Fix incorrect commentary
Fix c&p error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index c326a4c..1ff1eac 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ + /* Disable AXI interface by asserting FPGA resets */ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ @@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); |