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| author | Simon Glass <sjg@chromium.org> | 2015-03-26 15:29:29 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-18 17:11:15 (GMT) |
| commit | 90b16d1491facd55909bdeca1326766dd5d0b925 (patch) | |
| tree | 4452fcddff86abfc0b92d275193aa5dfb39fe8ee /arch/avr32 | |
| parent | a274e9cac55de3c8ca4e877912a260fb646df38d (diff) | |
| download | u-boot-fsl-qoriq-90b16d1491facd55909bdeca1326766dd5d0b925.tar.xz | |
x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.
Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/avr32')
0 files changed, 0 insertions, 0 deletions