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| author | Sonic Zhang <sonic.zhang@analog.com> | 2012-08-16 03:56:14 (GMT) |
|---|---|---|
| committer | sonic <sonic@sonic-linuxvm.(none)> | 2013-03-04 05:42:06 (GMT) |
| commit | a2979dcdbeb39a01dc888090d2c736c2ad3f548d (patch) | |
| tree | a682537c30714af45a998e2c3cedbe495de05e52 /arch/blackfin/cpu/initcode.h | |
| parent | 3ead92c571e7e17ca1c525c0fcd40e58901c5655 (diff) | |
| download | u-boot-fsl-qoriq-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.tar.xz | |
blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Diffstat (limited to 'arch/blackfin/cpu/initcode.h')
| -rw-r--r-- | arch/blackfin/cpu/initcode.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h index e0aad6d..1fec7f3 100644 --- a/arch/blackfin/cpu/initcode.h +++ b/arch/blackfin/cpu/initcode.h @@ -15,6 +15,8 @@ # define serial_putc(c) #endif +#ifndef __ADSPBF60x__ + #ifndef CONFIG_EBIU_RSTCTL_VAL # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ #endif @@ -30,6 +32,8 @@ # error invalid EBIU_DDRQUE value: must not set reserved bits #endif +#endif /* __ADSPBF60x__ */ + __attribute__((always_inline)) static inline void program_async_controller(ADI_BOOT_DATA *bs) { @@ -45,10 +49,13 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('a'); +#ifdef __ADSPBF60x__ /* Program the async banks controller. */ +#ifdef EBIU_AMGCTL bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); +#endif serial_putc('b'); @@ -66,6 +73,51 @@ program_async_controller(ADI_BOOT_DATA *bs) #endif serial_putc('c'); + +#else /* __ADSPBF60x__ */ + /* Program the static memory controller. */ +# ifdef CONFIG_SMC_GCTL_VAL + bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL); +# endif +# ifdef CONFIG_SMC_B0CTL_VAL + bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL); +# endif +# ifdef CONFIG_SMC_B0TIM_VAL + bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL); +# endif +# ifdef CONFIG_SMC_B0ETIM_VAL + bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B1CTL_VAL + bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL); +# endif +# ifdef CONFIG_SMC_B1TIM_VAL + bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL); +# endif +# ifdef CONFIG_SMC_B1ETIM_VAL + bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B2CTL_VAL + bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL); +# endif +# ifdef CONFIG_SMC_B2TIM_VAL + bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL); +# endif +# ifdef CONFIG_SMC_B2ETIM_VAL + bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL); +# endif +# ifdef CONFIG_SMC_B3CTL_VAL + bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL); +# endif +# ifdef CONFIG_SMC_B3TIM_VAL + bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL); +# endif +# ifdef CONFIG_SMC_B3ETIM_VAL + bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL); +# endif + +#endif + serial_putc('d'); } #endif |