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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2015-12-16 08:45:41 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-01-25 16:24:15 (GMT) |
| commit | a994b3deb00bf3177cdf9f92060baec4f640f466 (patch) | |
| tree | e7e7a70b20a26ab4d63ff55ea91b867343a03b23 /arch/powerpc/cpu/mpc86xx | |
| parent | 6f14e257c472c895499c186b602861e90f2656b5 (diff) | |
| download | u-boot-fsl-qoriq-a994b3deb00bf3177cdf9f92060baec4f640f466.tar.xz | |
driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.
When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx')
0 files changed, 0 insertions, 0 deletions