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| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2013-08-16 07:10:37 (GMT) |
|---|---|---|
| committer | Heiko Schocher <hs@denx.de> | 2013-08-20 09:15:31 (GMT) |
| commit | 9c3f77eb3bc0e1e24fc66bd41655fecddb6403ec (patch) | |
| tree | c547108292e7d49f91e9c1eb06d06d4de96a7d17 /arch/powerpc/include/asm/fsl_i2c.h | |
| parent | b8ce3343b64434b95b9a25dea0534bf9f1593e8c (diff) | |
| download | u-boot-fsl-qoriq-9c3f77eb3bc0e1e24fc66bd41655fecddb6403ec.tar.xz | |
fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.
At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.
The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_i2c.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_i2c.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index 4f71341..d6537fd 100644 --- a/arch/powerpc/include/asm/fsl_i2c.h +++ b/arch/powerpc/include/asm/fsl_i2c.h @@ -54,6 +54,7 @@ typedef struct fsl_i2c { #define I2C_CR_MTX 0x10 #define I2C_CR_TXAK 0x08 #define I2C_CR_RSTA 0x04 +#define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ #define I2C_CR_BCST 0x01 u8 sr; /* I2C status register */ |