diff options
author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2013-11-22 09:39:10 (GMT) |
---|---|---|
committer | York Sun <yorksun@freescale.com> | 2013-11-25 19:44:25 (GMT) |
commit | 629d6b32d6b9452b852fe79a195cca5b897fcad3 (patch) | |
tree | 12bb70fc7aae18ac00d1354f85d2245df85701a7 /arch/powerpc/include | |
parent | 82a55c1ef87bb6c596b19e83685cc4cbf0344cb3 (diff) | |
download | u-boot-fsl-qoriq-629d6b32d6b9452b852fe79a195cca5b897fcad3.tar.xz |
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 44 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 16 | ||||
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 2 |
3 files changed, 62 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 047fdf1..99e16bd 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -718,6 +718,50 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define CONFIG_E6500 +#define CONFIG_SYS_PPC64 /* 64-bit core */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCI_VER_3_X +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_SRIO_LIODN +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#endif +#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_PME_PLAT_CLK_DIV 1 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ISBC_VER 2 + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 882b0b1..672e8c6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,6 +1759,12 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 @@ -1822,6 +1828,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 +#endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -2818,6 +2833,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 81f9d38..831804c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1127,6 +1127,8 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T2080 0x853000 +#define SVR_T2081 0x853100 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 |