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| author | Simon Glass <sjg@chromium.org> | 2015-01-01 23:18:06 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-13 15:25:00 (GMT) |
| commit | 3a5659f7cfc0fd99b57fe2ed9e4a9ebde7cf8491 (patch) | |
| tree | 66bb7b016eb5b8fca58067837ae8013316914fb3 /arch/x86/cpu | |
| parent | 9a99caf3f3e220d744525d492f7e72a5c8756374 (diff) | |
| download | u-boot-fsl-qoriq-3a5659f7cfc0fd99b57fe2ed9e4a9ebde7cf8491.tar.xz | |
x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 969b07b..0543e06 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -49,27 +49,6 @@ static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) pci_hose_write_config_byte(hose, dev, 0xdc, reg8); } -static void set_var_mtrr( - unsigned reg, unsigned base, unsigned size, unsigned type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - wrmsr(MTRRphysBase_MSR(reg), base | type, 0); - wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid, - (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1); -} - -static void enable_rom_caching(void) -{ - disable_caches(); - set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT); - enable_caches(); - - /* Enable Variable MTRRs */ - wrmsr(MTRRdefType_MSR, 0x800, 0); -} - static int set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -165,10 +144,6 @@ int arch_cpu_init(void) /* This is already done in start.S, but let's do it in C */ enable_port80_on_lpc(hose, PCH_LPC_DEV); - /* already done in car.S */ - if (false) - enable_rom_caching(); - set_spi_speed(); /* |