diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 14:35:06 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 08:39:39 (GMT) |
| commit | 05b98ec3468547057666dd685b2a1615298c24cc (patch) | |
| tree | f6b4914a6cc6423e573dbf059ce8b8ae057f1659 /arch/x86/include/asm | |
| parent | 5910955f3cf685c1ca4e4abd1546fc59da55239a (diff) | |
| download | u-boot-fsl-qoriq-05b98ec3468547057666dd685b2a1615298c24cc.tar.xz | |
x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/arch-quark/device.h | 70 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-quark/quark.h | 15 |
2 files changed, 70 insertions, 15 deletions
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h index 4af3ded..7882f33 100644 --- a/arch/x86/include/asm/arch-quark/device.h +++ b/arch/x86/include/asm/arch-quark/device.h @@ -9,20 +9,60 @@ #include <pci.h> -#define QUARK_HOST_BRIDGE PCI_BDF(0, 0, 0) -#define QUARK_MMC_SDIO PCI_BDF(0, 20, 0) -#define QUARK_UART0 PCI_BDF(0, 20, 1) -#define QUARK_USB_DEVICE PCI_BDF(0, 20, 2) -#define QUARK_USB_EHCI PCI_BDF(0, 20, 3) -#define QUARK_USB_OHCI PCI_BDF(0, 20, 4) -#define QUARK_UART1 PCI_BDF(0, 20, 5) -#define QUARK_EMAC0 PCI_BDF(0, 20, 6) -#define QUARK_EMAC1 PCI_BDF(0, 20, 7) -#define QUARK_SPI0 PCI_BDF(0, 21, 0) -#define QUARK_SPI1 PCI_BDF(0, 21, 1) -#define QUARK_I2C_GPIO PCI_BDF(0, 21, 2) -#define QUARK_PCIE0 PCI_BDF(0, 23, 0) -#define QUARK_PCIE1 PCI_BDF(0, 23, 1) -#define QUARK_LEGACY_BRIDGE PCI_BDF(0, 31, 0) +#define QUARK_HOST_BRIDGE_DEV 0 +#define QUARK_HOST_BRIDGE_FUNC 0 + +#define QUARK_DEV_20 20 +#define QUARK_MMC_SDIO_FUNC 0 +#define QUARK_UART0_FUNC 1 +#define QUARK_USB_DEVICE_FUNC 2 +#define QUARK_USB_EHCI_FUNC 3 +#define QUARK_USB_OHCI_FUNC 4 +#define QUARK_UART1_FUNC 5 +#define QUARK_EMAC0_FUNC 6 +#define QUARK_EMAC1_FUNC 7 + +#define QUARK_DEV_21 21 +#define QUARK_SPI0_FUNC 0 +#define QUARK_SPI1_FUNC 1 +#define QUARK_I2C_GPIO_FUNC 2 + +#define QUARK_DEV_23 23 +#define QUARK_PCIE0_FUNC 0 +#define QUARK_PCIE1_FUNC 1 + +#define QUARK_LGC_BRIDGE_DEV 31 +#define QUARK_LGC_BRIDGE_FUNC 0 + +#define QUARK_HOST_BRIDGE \ + PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC) +#define QUARK_MMC_SDIO \ + PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC) +#define QUARK_UART0 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC) +#define QUARK_USB_DEVICE \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC) +#define QUARK_USB_EHCI \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC) +#define QUARK_USB_OHCI \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC) +#define QUARK_UART1 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC) +#define QUARK_EMAC0 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC) +#define QUARK_EMAC1 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC) +#define QUARK_SPI0 \ + PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC) +#define QUARK_SPI1 \ + PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC) +#define QUARK_I2C_GPIO \ + PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC) +#define QUARK_PCIE0 \ + PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC) +#define QUARK_PCIE1 \ + PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC) +#define QUARK_LEGACY_BRIDGE \ + PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC) #endif /* _QUARK_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index 6dd02fd..c997928 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -76,4 +76,19 @@ #define LB_BC 0xd8 #define LB_RCBA 0xf0 +#ifndef __ASSEMBLY__ + +/* Root Complex Register Block */ +struct quark_rcba { + u32 rctl; + u32 esd; + u32 rsvd1[3150]; + u16 rmu_ir; + u16 d23_ir; + u16 core_ir; + u16 d20d21_ir; +}; + +#endif /* __ASSEMBLY__ */ + #endif /* _QUARK_H_ */ |