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author | Michal Simek <michal.simek@xilinx.com> | 2014-02-05 07:06:29 (GMT) |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-02-13 14:33:00 (GMT) |
commit | 38716189d439c3ed8707e7bc1f430322ba7a810d (patch) | |
tree | 642ae8ba2b04008b6009db13d808ae4dc3dc268b /arch | |
parent | dfa94058f550e06405e80df4fb277fd306a77cbd (diff) | |
download | u-boot-fsl-qoriq-38716189d439c3ed8707e7bc1f430322ba7a810d.tar.xz |
zynq: Fix elf header generation
This patch is here because of:
"arm: keep all sections in ELF file"
(sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7)
Our tools expect to have elf with only LOAD header.
Without this fix also PHDR, INTERP and DYNAMIC headers
are available in ELF.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/armv7/zynq/u-boot.lds | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds new file mode 100644 index 0000000..a68b050 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /* + * Zynq needs to discard more sections because the user + * is expected to pass this image on to tools for boot.bin + * generation that require them to be dropped. + */ + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} |