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authorScott Wood <scottwood@freescale.com>2013-05-15 22:50:13 (GMT)
committerAndy Fleming <afleming@freescale.com>2013-06-20 22:08:49 (GMT)
commit8212519254bc3ea94d959f56f10061849aa07b26 (patch)
tree9e9215a35509b017d7927f7ca213fa47dcc1a423 /arch
parent362ee04b797d02117e48312010974d69c325be60 (diff)
downloadu-boot-fsl-qoriq-8212519254bc3ea94d959f56f10061849aa07b26.tar.xz
powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c3
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h2
3 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 422782c..a7ed877 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -258,6 +258,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+ puts("Work-around for Erratum A006593 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 0990141..3c8f59c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -172,6 +172,9 @@ static void enable_cpc(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+ setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
+#endif
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6b1d3c4..1d46b14 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -555,6 +555,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -576,6 +577,7 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860