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author | Tom Rini <trini@konsulko.com> | 2015-09-07 12:56:08 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2015-09-07 12:56:08 (GMT) |
commit | a6003397f7b74f7af6c21954073e046de08f43c9 (patch) | |
tree | 49fd7e2356979bea9d9f4fffe1875ec02e5059b2 /arch | |
parent | a883f83e6d62fef1830b1634ccb72535c43696f7 (diff) | |
parent | a7ed0ac2620b00c6eb85227f3c66bc169ad11f44 (diff) | |
download | u-boot-fsl-qoriq-a6003397f7b74f7af6c21954073e046de08f43c9.tar.xz |
Merge git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 2 | ||||
-rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 61 | ||||
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 53 | ||||
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_sockit.dts | 92 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 21 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/dwmmc.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/misc.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/reset_manager.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/spl.c | 2 |
10 files changed, 241 insertions, 12 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c598f5e..8085a24 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -539,6 +539,8 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 select SUPPORT_SPL + select OF_CONTROL + select SPL_OF_CONTROL select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3babe65..f2e18a5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -60,7 +60,10 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 0000000..b649c9a --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -0,0 +1,61 @@ +/* + * Copyright Altera Corporation (C) 2015 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE0-Nano(Atlas)"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts new file mode 100644 index 0000000..e1e3d73 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "DENX MCVEVK"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac0; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + bus-width = <8>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts new file mode 100644 index 0000000..d7c41c8 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 690e362..089280a 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -18,15 +18,33 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_DENX_MCVEVK + bool "DENX MCVEVK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_TERASIC_DE0_NANO + bool "Terasic DE0-Nano-Atlas (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_TERASIC_SOCKIT + bool "Terasic SoCkit (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC default "socfpga" @@ -34,5 +52,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT endif diff --git a/arch/arm/mach-socfpga/include/mach/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h index 945eb64..e8ba901 100644 --- a/arch/arm/mach-socfpga/include/mach/dwmmc.h +++ b/arch/arm/mach-socfpga/include/mach/dwmmc.h @@ -7,6 +7,6 @@ #ifndef _SOCFPGA_DWMMC_H_ #define _SOCFPGA_DWMMC_H_ -extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); +int socfpga_dwmmc_init(const void *blob); #endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 6128d54..0940cc5 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -125,14 +125,7 @@ int cpu_eth_init(bd_t *bis) */ int cpu_mmc_init(bd_t *bis) { -/* - * FIXME: Temporarily define CONFIG_HPS_SDMMC_BUSWIDTH to prevent breakage - * due to missing patches in u-boot/master . The upcoming patch will - * switch this to OF probing, so this whole block will go away. - */ -#define CONFIG_HPS_SDMMC_BUSWIDTH 8 - return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, - CONFIG_HPS_SDMMC_BUSWIDTH, 0); + return socfpga_dwmmc_init(gd->fdt_blob); } #endif diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 1186358..b6beaa2 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,13 +7,16 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/reset_manager.h> #include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) @@ -97,6 +100,9 @@ void socfpga_bridges_reset(int enable) /* brdmodrst */ writel(0xffffffff, &reset_manager_base->brg_mod_reset); } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { /* FPGA not ready, do nothing. */ diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 13ec24b..775a827 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -180,6 +180,4 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); - - board_init_r(NULL, 0); } |