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authorAneesh Bansal <aneesh.bansal@freescale.com>2014-03-11 18:37:27 (GMT)
committerYork Sun <yorksun@freescale.com>2014-04-23 00:58:46 (GMT)
commitf978f7c203a6ea8a9bdc101a12486d6903fd8162 (patch)
tree660f9c067b6287fab5124c2982ffa0c5f7460f24 /arch
parent7efb4b51975409fb922e9f9bfec21a7affb6f83f (diff)
downloadu-boot-fsl-qoriq-f978f7c203a6ea8a9bdc101a12486d6903fd8162.tar.xz
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S9
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h2
2 files changed, 4 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 6b0380f..9eee549 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -467,7 +467,8 @@ nexti: mflr r1 /* R1 = our PC */
2: cmpw r3, r4
blt 1b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
+ !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
@@ -488,12 +489,6 @@ nexti: mflr r1 /* R1 = our PC */
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 4c7f0b1..3dce1d2 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -10,6 +10,8 @@
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
+#elif defined(CONFIG_BSC9132QDS)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif