diff options
author | Stefan Roese <sr@denx.de> | 2015-03-25 12:35:15 (GMT) |
---|---|---|
committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-07-23 08:39:35 (GMT) |
commit | 9e30b31d20f0b793465d07f056b3d9885f578c0d (patch) | |
tree | 1e98a4d567883c7ddc19c414bc50f389091dbfcb /board/Marvell/db-88f6820-gp | |
parent | ad6ac7aa0002915bf2a285c85a8e96a0f8c2b6aa (diff) | |
download | u-boot-fsl-qoriq-9e30b31d20f0b793465d07f056b3d9885f578c0d.tar.xz |
arm: mvebu: db-88f6820: Add SPL support with DDR init code
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/Marvell/db-88f6820-gp')
-rw-r--r-- | board/Marvell/db-88f6820-gp/README | 18 | ||||
-rw-r--r-- | board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 31 | ||||
-rw-r--r-- | board/Marvell/db-88f6820-gp/kwbimage.cfg | 2 |
3 files changed, 50 insertions, 1 deletions
diff --git a/board/Marvell/db-88f6820-gp/README b/board/Marvell/db-88f6820-gp/README new file mode 100644 index 0000000..9bea5b3 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/README @@ -0,0 +1,18 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +To update the SPI NOR flash, please use the following +command: + +=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ +sf update 2000000 0 60000 + +Note that the original Marvell U-Boot seems to have +problems with the "sf update" command. This does not +work reliable. So here this command should be used: + +=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ +sf erase 0 60000;sf write 2000000 0 60000 diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 51ac495..e661fa1 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -11,6 +11,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" + DECLARE_GLOBAL_DATA_PTR; #define BIT(nr) (1UL << (nr)) @@ -54,6 +56,35 @@ static struct marvell_io_exp io_exp[] = { { 0x21, 3, 0xC0 } /* Output Data, register#1 */ }; +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map board_topology_map = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1866L, /* speed_bin */ + BUS_WIDTH_8, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_LOW} }, /* temperature */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + int board_early_init_f(void) { /* Configure MPP */ diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg index e812454..cc05792 100644 --- a/board/Marvell/db-88f6820-gp/kwbimage.cfg +++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 |