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| author | Stefan Roese <sr@denx.de> | 2017-03-10 14:40:31 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2017-03-23 09:52:28 (GMT) |
| commit | 1304f4bb8ed0971ca28e8b519b831c9f99295286 (patch) | |
| tree | 103319945fb9d5a4515d0a52f379cf1e94d0ce4d /board/Synology | |
| parent | 2399e40120f7a04fc24d496f486e5e406852538f (diff) | |
| download | u-boot-fsl-qoriq-1304f4bb8ed0971ca28e8b519b831c9f99295286.tar.xz | |
arm: mvebu: theadorable: Add board-specific PEX detection pulse width
Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/Synology')
0 files changed, 0 insertions, 0 deletions