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author | York Sun <yorksun@freescale.com> | 2012-12-23 19:25:27 (GMT) |
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committer | Andy Fleming <afleming@freescale.com> | 2013-01-30 17:25:11 (GMT) |
commit | b5b06fb7b04a93ea48638d4d2ba1932051a28f64 (patch) | |
tree | 1724bf4db2f33fecfe09628de1faec621b251391 /board/freescale/b4860qds/b4860qds_crossbar_con.h | |
parent | db9a807054ec82f4f6352677ea8b5d8176050a8a (diff) | |
download | u-boot-fsl-qoriq-b5b06fb7b04a93ea48638d4d2ba1932051a28f64.tar.xz |
powerpc/b4860qds: Added Support for B4860QDS
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.
B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds/b4860qds_crossbar_con.h')
-rw-r--r-- | board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h new file mode 100644 index 0000000..994dec5 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -0,0 +1,67 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CROSSBAR_CONNECTIONS_H__ +#define __CROSSBAR_CONNECTIONS_H__ + +#define NUM_CON_VSC3316 8 +#define NUM_CON_VSC3308 4 + +static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, + {5, 11}, {4, 5}, {2, 6}, {12, 9} }; + +static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1}, + {5, 15}, {4, 14}, {2, 12}, {12, 13} }; + +static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif +static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, + {11, 11}, {5, 10}, {6, 3}, {9, 12} }; + +static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif + +static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; + +static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} }; + +static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; + +static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} }; + +#endif |