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author | Stephen George <stephen.george@freescale.com> | 2013-03-25 07:40:12 (GMT) |
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committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 21:54:12 (GMT) |
commit | 49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (patch) | |
tree | 07118135410c7b399c8ac780b6fa803ceebdfaea /board/freescale/b4860qds/tlb.c | |
parent | 94025b1cd8d9959ebf987a7f6382d513c606ecf1 (diff) | |
download | u-boot-fsl-qoriq-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.xz |
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds/tlb.c')
-rw-r--r-- | board/freescale/b4860qds/tlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 6d634bf..29cc41b 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -106,7 +106,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4M, 1), + 0, 10, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* |