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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2016-01-06 03:26:51 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-01-25 16:24:14 (GMT) |
| commit | 0d3972cfcd6dff18d110d2ee01ad99e3623bfd45 (patch) | |
| tree | cf44538dad352ebcedef94d99a03c432f6d736e8 /board/freescale/common | |
| parent | 12f229ea8f6c8e20f8fd07906eafc853c4c354a9 (diff) | |
| download | u-boot-fsl-qoriq-0d3972cfcd6dff18d110d2ee01ad99e3623bfd45.tar.xz | |
fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/common')
0 files changed, 0 insertions, 0 deletions