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| author | Tom Rini <trini@ti.com> | 2014-09-26 13:57:52 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-09-26 13:57:52 (GMT) |
| commit | 2c2277f15cbaa9533ef8aead7328c3f605251147 (patch) | |
| tree | 9e7ee343a1f75ecdd57a7fa8025eab2464654ecb /board/freescale/ls1021aqds/ddr.c | |
| parent | 2c3dc792b6df16970077c0d64085e29f1f85d4c8 (diff) | |
| parent | c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76 (diff) | |
| download | u-boot-fsl-qoriq-2c2277f15cbaa9533ef8aead7328c3f605251147.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'board/freescale/ls1021aqds/ddr.c')
| -rw-r--r-- | board/freescale/ls1021aqds/ddr.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 679c654..5898e33 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -79,7 +79,6 @@ found: */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; - popts->cswl_override = DDR_CSWL_CS0; /* * Rtt and Rtt_WR override @@ -89,9 +88,17 @@ found: /* Enable ZQ calibration */ popts->zq_en = 1; +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #ifdef CONFIG_SYS_DDR_RAW_TIMING |