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authorDave Liu <daveliu@freescale.com>2008-10-28 09:46:23 (GMT)
committerJon Loeliger <jdl@freescale.com>2008-10-30 15:27:44 (GMT)
commit137a2dfd11ac51ae3154f13f323609b33a4a072e (patch)
tree9d8130332dfb50101c17809d5b42a96749b2016c /board/freescale/mpc8641hpcn
parentdc2adad85bf580d65916c940683f6e9671e8a5dd (diff)
downloadu-boot-fsl-qoriq-137a2dfd11ac51ae3154f13f323609b33a4a072e.tar.xz
86xx: remove the unused ddr_enable_ecc in the board file
The DDR controller of 86xx processors have the ECC data init feature, and the new DDR code is using the feature, we don't need the way with DMA to init memory again. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
Diffstat (limited to 'board/freescale/mpc8641hpcn')
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 6b4d6ce..0069b9c 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -33,10 +33,6 @@
#include "../common/pixis.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
long int fixed_sdram(void);
int board_early_init_f(void)
@@ -70,13 +66,6 @@ initdram(int board_type)
return dram_size;
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
puts(" DDR: ");
return dram_size;
}