diff options
| author | Heiko Schocher <hs@denx.de> | 2017-06-27 14:49:14 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-07-03 21:35:28 (GMT) |
| commit | 98f705c9cefdfdba62c069821bbba10273a0a8ed (patch) | |
| tree | 48a56e8496a9b6f5bcf523916ace5445489d79c7 /board/gdsys | |
| parent | d4db3b86a5e090e21db710bedbbe3e50d4c56428 (diff) | |
| download | u-boot-fsl-qoriq-98f705c9cefdfdba62c069821bbba10273a0a8ed.tar.xz | |
powerpc: remove 4xx support
There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/gdsys')
34 files changed, 0 insertions, 3175 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c deleted file mode 100644 index 35fa06a..0000000 --- a/board/gdsys/405ep/405ep.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/global_data.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define REFLECTION_TESTPATTERN 0xdede -#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) - -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI -#define REFLECTION_TESTREG reflection_low -#else -#define REFLECTION_TESTREG reflection_high -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int get_fpga_state(unsigned dev) -{ - return gd->arch.fpga_state[dev]; -} - -int board_early_init_f(void) -{ - unsigned k; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - return 0; -} - -int board_early_init_r(void) -{ - unsigned k; - unsigned ctr; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - /* - * reset FPGA - */ - gd405ep_init(); - - gd405ep_set_fpga_reset(1); - - gd405ep_setup_hw(); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ctr = 0; - while (!gd405ep_get_fpga_done(k)) { - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_DONE_FAILED; - break; - } - } - } - - udelay(10); - - gd405ep_set_fpga_reset(0); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - /* - * wait for fpga out of reset - */ - ctr = 0; - while (1) { - u16 val; - - FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - - FPGA_GET_REG(k, REFLECTION_TESTREG, &val); - if (val == REFLECTION_TESTPATTERN_INV) - break; - - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_REFLECTION_FAILED; - break; - } - } - } - - return 0; -} diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h deleted file mode 100644 index 5647dbc..0000000 --- a/board/gdsys/405ep/405ep.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __405EP_H_ -#define __405EP_H_ - -/* functions to be provided by board implementation */ -void gd405ep_init(void); -void gd405ep_set_fpga_reset(unsigned state); -void gd405ep_setup_hw(void); -int gd405ep_get_fpga_done(unsigned fpga); - -#endif /* __405EP_H_ */ diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig deleted file mode 100644 index 20cb80f..0000000 --- a/board/gdsys/405ep/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -if TARGET_DLVISION_10G - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "dlvision-10g" - -endif - -if TARGET_IO - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "io" - -endif - -if TARGET_IOCON - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "iocon" - -endif - -if TARGET_NEO - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "neo" - -endif diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS deleted file mode 100644 index 1403880..0000000 --- a/board/gdsys/405ep/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -405EP BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/405ep/ -F: include/configs/dlvision-10g.h -F: configs/dlvision-10g_defconfig -F: include/configs/io.h -F: configs/io_defconfig -F: include/configs/iocon.h -F: configs/iocon_defconfig -F: include/configs/neo.h -F: configs/neo_defconfig diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile deleted file mode 100644 index 857ec04..0000000 --- a/board/gdsys/405ep/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := 405ep.o -obj-$(CONFIG_NEO) += neo.o -obj-$(CONFIG_IO) += io.o -obj-$(CONFIG_IOCON) += iocon.o -obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c deleted file mode 100644 index b531786..0000000 --- a/board/gdsys/405ep/dlvision-10g.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#include "../common/osd.h" - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) - -#define LATCH2_MC2_PRESENT_N 0x0080 - -enum { - UNITTYPE_MAIN = 1<<0, - UNITTYPE_SERVER = 1<<1, - UNITTYPE_DISPLAYPORT = 1<<2, -}; - -enum { - HWVER_101 = 0, - HWVER_110 = 1, - HWVER_130 = 2, - HWVER_140 = 3, - HWVER_150 = 4, - HWVER_160 = 5, - HWVER_170 = 6, -}; - -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, -}; - -enum { - SYSCLK_156250 = 2, -}; - -enum { - RAM_NONE = 0, - RAM_DDR2_32 = 1, - RAM_DDR2_64 = 2, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -static unsigned int get_hwver(void) -{ - u16 latch3 = in_le16((void *)LATCH3_BASE); - - return latch3 & 0x0003; -} - -static unsigned int get_mc2_present(void) -{ - u16 latch2 = in_le16((void *)LATCH2_BASE); - - return !(latch2 & LATCH2_MC2_PRESENT_N); -} - -static void print_fpga_info(unsigned dev) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_rs232; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - int fpga_state = get_fpga_state(dev); - - printf("FPGA%d: ", dev); - - FPGA_GET_REG(dev, versions, &versions); - FPGA_GET_REG(dev, fpga_version, &fpga_version); - FPGA_GET_REG(dev, fpga_features, &fpga_features); - - hardware_version = versions & 0x000f; - - if (fpga_state - && !((hardware_version == HWVER_101) - && (fpga_state == FPGA_STATE_DONE_FAILED))) { - puts("not available\n"); - if (fpga_state & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); - return; - } - - unit_type = (versions >> 4) & 0x000f; - hardware_version = versions & 0x000f; - feature_rs232 = fpga_features & (1<<11); - feature_audio = (fpga_features >> 9) & 0x0003; - feature_sysclock = (fpga_features >> 7) & 0x0003; - feature_ramconfig = (fpga_features >> 5) & 0x0003; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features >> 2) & 0x0003; - feature_video_channels = fpga_features & 0x0003; - - if (unit_type & UNITTYPE_MAIN) - printf("Mainchannel "); - else - printf("Videochannel "); - - if (unit_type & UNITTYPE_SERVER) - printf("Serverside "); - else - printf("Userside "); - - if (unit_type & UNITTYPE_DISPLAYPORT) - printf("DisplayPort"); - else - printf("DVI-DL"); - - switch (hardware_version) { - case HWVER_101: - printf(" HW-Ver 1.01\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10-1.20\n"); - break; - - case HWVER_130: - printf(" HW-Ver 1.30\n"); - break; - - case HWVER_140: - printf(" HW-Ver 1.40-1.43\n"); - break; - - case HWVER_150: - printf(" HW-Ver 1.50\n"); - break; - - case HWVER_160: - printf(" HW-Ver 1.60-1.61\n"); - break; - - case HWVER_170: - printf(" HW-Ver 1.70\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %sRS232", feature_rs232 ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } - - switch (feature_sysclock) { - case SYSCLK_156250: - printf(", clock 156.25 MHz"); - break; - - default: - printf(", clock %d(not supported)", feature_sysclock); - break; - } - - puts(",\n "); - - switch (feature_ramconfig) { - case RAM_NONE: - printf("no RAM"); - break; - - case RAM_DDR2_32: - printf("RAM 32 bit DDR2"); - break; - - case RAM_DDR2_64: - printf("RAM 64 bit DDR2"); - break; - - default: - printf("RAM %d(not supported)", feature_ramconfig); - break; - } - - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); - - printf(", %d video channel(s)\n", feature_video_channels); -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: "); - - puts("DLVision 10G"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -int last_stage_init(void) -{ - u16 versions; - - FPGA_GET_REG(0, versions, &versions); - - print_fpga_info(0); - if (get_mc2_present()) - print_fpga_info(1); - - if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER) - return 0; - - if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) - osd_probe(0); - - if (get_mc2_present() && - (!get_fpga_state(1) || (get_hwver() == HWVER_101))) - osd_probe(1); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); -} diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c deleted file mode 100644 index 1484469..0000000 --- a/board/gdsys/405ep/io.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include <miiphy.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -#define PHYREG_CONTROL 0 -#define PHYREG_PAGE_ADDRESS 22 -#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 -#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 - -enum { - UNITTYPE_CCD_SWITCH = 1, -}; - -enum { - HWVER_100 = 0, - HWVER_110 = 1, - HWVER_121 = 2, - HWVER_122 = 3, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -int configure_gbit_phy(unsigned char addr) -{ - unsigned short value; - - /* select page 2 */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* disable SGMII autonegotiation */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a)) - goto err_out; - /* select page 0 */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch from powerdown to normal operation */ - if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value)) - goto err_out; - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004)) - goto err_out; - /* reset phy so settings take effect */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_CONTROL, 0x9140)) - goto err_out; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: CATCenter Io"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(void) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - unsigned feature_expansion; - - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - feature_expansion = fpga_features & (1<<15); - - puts("FPGA: "); - - switch (unit_type) { - case UNITTYPE_CCD_SWITCH: - printf("CCD-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; - - case HWVER_121: - printf(" HW-Ver 1.21\n"); - break; - - case HWVER_122: - printf(" HW-Ver 1.22\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)", feature_channels); - - printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); -} - -/* - * setup Gbit PHYs - */ -int last_stage_init(void) -{ - unsigned int k; - - print_fpga_info(); - - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) - configure_gbit_phy(k); - - /* take fpga serdes blocks out of reset */ - FPGA_SET_REG(0, quad_serdes_reset, 0); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); -} diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c deleted file mode 100644 index 7db0e29..0000000 --- a/board/gdsys/405ep/iocon.c +++ /dev/null @@ -1,673 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#include "../common/osd.h" -#include "../common/mclink.h" -#include "../common/phy.h" - -#include <i2c.h> -#include <pca953x.h> -#include <pca9698.h> - -#include <miiphy.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -#define MAX_MUX_CHANNELS 2 - -enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, -}; - -enum { - HWVER_100 = 0, - HWVER_104 = 1, - HWVER_110 = 2, - HWVER_120 = 3, - HWVER_200 = 4, - HWVER_210 = 5, - HWVER_220 = 6, - HWVER_230 = 7, -}; - -enum { - FPGA_HWVER_200 = 0, - FPGA_HWVER_210 = 1, -}; - -enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA = 1, - COMPRESSION_TYPE1_TYPE2_DELTA = 3, -}; - -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, -}; - -enum { - SYSCLK_147456 = 0, -}; - -enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, -}; - -enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, -}; - -enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, -}; - -enum { - GPIO_MDC = 1 << 14, - GPIO_MDIO = 1 << 15, -}; - -unsigned int mclink_fpgacount; -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - int res; - - switch (fpga) { - case 0: - out_le16(reg, data); - break; - default: - res = mclink_send(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_send reg %02lx data %04x returned %d\n", - regoff, data, res); - return res; - } - break; - } - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - int res; - - switch (fpga) { - case 0: - *data = in_le16(reg); - break; - default: - if (fpga > mclink_fpgacount) - return -EINVAL; - res = mclink_receive(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_receive reg %02lx returned %d\n", - regoff, res); - return res; - } - } - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: "); - - puts("IoCon"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(unsigned int fpga, bool rgmii2_present) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - - int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM; - - FPGA_GET_REG(fpga, versions, &versions); - FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - if (legacy) - printf("legacy "); - - switch (unit_type) { - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); - break; - - case UNITTYPE_VIDEO_USER: - printf("Videochannel"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - if (unit_type == UNITTYPE_MAIN_USER) { - if (legacy) - hardware_version = - (in_le16((void *)LATCH2_BASE)>>8) & 0x0f; - else - hardware_version = - (!!pca9698_get_value(0x20, 24) << 0) - | (!!pca9698_get_value(0x20, 25) << 1) - | (!!pca9698_get_value(0x20, 26) << 2) - | (!!pca9698_get_value(0x20, 27) << 3); - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00,"); - break; - - case HWVER_104: - printf(" HW-Ver 1.04,"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10,"); - break; - - case HWVER_120: - printf(" HW-Ver 1.20-1.21,"); - break; - - case HWVER_200: - printf(" HW-Ver 2.00,"); - break; - - case HWVER_210: - printf(" HW-Ver 2.10,"); - break; - - case HWVER_220: - printf(" HW-Ver 2.20,"); - break; - - case HWVER_230: - printf(" HW-Ver 2.30,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - if (rgmii2_present) - printf(" RGMII2,"); - } - - if (unit_type == UNITTYPE_VIDEO_USER) { - hardware_version = versions & 0x000f; - switch (hardware_version) { - case FPGA_HWVER_200: - printf(" HW-Ver 2.00,"); - break; - - case FPGA_HWVER_210: - printf(" HW-Ver 2.10,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - } - - printf(" FPGA V %d.%02d\n features:", - fpga_version / 100, fpga_version % 100); - - - switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); - break; - - case COMPRESSION_TYPE1_DELTA: - printf(" type1-deltacompression"); - break; - - case COMPRESSION_TYPE1_TYPE2_DELTA: - printf(" type1-deltacompression, type2-inlinecompression"); - break; - - default: - printf(" compression %d(not supported)", feature_compression); - break; - } - - printf(", %sosd", feature_osd ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } - - puts(",\n "); - - switch (feature_sysclock) { - case SYSCLK_147456: - printf("clock 147.456 MHz"); - break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; - } - - switch (feature_ramconfig) { - case RAM_DDR2_32: - printf(", RAM 32 bit DDR2"); - break; - - case RAM_DDR3_32: - printf(", RAM 32 bit DDR3"); - break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); - break; - } - - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); - - printf(", %d video channel(s)\n", feature_video_channels); -} - -int last_stage_init(void) -{ - int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - u16 fpga_features; - int feature_carrier_speed; - bool ch0_rgmii2_present = false; - - FPGA_GET_REG(0, fpga_features, &fpga_features); - feature_carrier_speed = fpga_features & (1<<4); - - if (!legacy) { - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 9, 1); - - ch0_rgmii2_present = !pca9698_get_value(0x20, 30); - } - - /* wait for FPGA done; then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; - - if (i2c_probe(mclink_controllers[k])) - continue; - - while (!(pca953x_get_val(mclink_controllers[k]) - & MCFPGA_DONE)) { - udelay(100000); - if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); - break; - } - } - - pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); - udelay(10); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, - MCFPGA_RESET_N); - } - - if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { - if ((mux_ch == 1) && !ch0_rgmii2_present) - continue; - - setup_88e1518(bb_miiphy_buses[0].name, mux_ch); - } - } - - /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); - - mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; - slaves = mclink_probe(); - mclink_fpgacount = 0; - - print_fpga_info(0, ch0_rgmii2_present); - osd_probe(0); - - if (slaves <= 0) - return 0; - - mclink_fpgacount = slaves; - - for (k = 1; k <= slaves; ++k) { - FPGA_GET_REG(k, fpga_features, &fpga_features); - feature_carrier_speed = fpga_features & (1<<4); - - print_fpga_info(k, false); - osd_probe(k); - if (feature_carrier_speed == CARRIER_SPEED_1G) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[k].name, - MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - setup_88e1518(bb_miiphy_buses[k].name, 0); - } - } - - return 0; -} - -/* - * provide access to fpga gpios (for I2C bitbang) - * (these may look all too simple but make iocon.h much more readable) - */ -void fpga_gpio_set(unsigned int bus, int pin) -{ - FPGA_SET_REG(bus, gpio.set, pin); -} - -void fpga_gpio_clear(unsigned int bus, int pin) -{ - FPGA_SET_REG(bus, gpio.clear, pin); -} - -int fpga_gpio_get(unsigned int bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus, gpio.read, &val); - - return val & pin; -} - -void gd405ep_init(void) -{ - unsigned int k; - - if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */ - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; - } else { - pca9698_direction_output(0x20, 4, 1); - } -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } - } else { - pca9698_set_value(0x20, 4, state ? 0 : 1); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) - return in_le16((void *)LATCH2_BASE) - & CONFIG_SYS_FPGA_DONE(fpga); - else - return pca9698_get_value(0x20, 20); -} - -/* - * FPGA MII bitbang implementation - */ - -struct fpga_mii { - unsigned fpga; - int mdio; -} fpga_mii[] = { - { 0, 1}, - { 1, 1}, - { 2, 1}, - { 3, 1}, -}; - -static int mii_dummy_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int mii_mdio_active(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (fpga_mii->mdio) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - return 0; -} - -static int mii_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - - return 0; -} - -static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - fpga_mii->mdio = v; - - return 0; -} - -static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - u16 gpio; - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); - - *v = ((gpio & GPIO_MDIO) != 0); - - return 0; -} - -static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); - - return 0; -} - -static int mii_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "board0", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[0], - }, - { - .name = "board1", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[1], - }, - { - .name = "board2", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[2], - }, - { - .name = "board3", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[3], - }, -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c deleted file mode 100644 index ad88af2..0000000 --- a/board/gdsys/405ep/neo.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -enum { - UNITTYPE_CCX16 = 1, - UNITTYPE_CCIP216 = 2, -}; - -enum { - HWVER_300 = 3, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: CATCenter Neo"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(void) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - int fpga_state = get_fpga_state(0); - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - - puts("FPGA: "); - if (fpga_state & FPGA_STATE_DONE_FAILED) { - printf(" done timed out\n"); - return; - } - - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { - printf(" refelectione test failed\n"); - return; - } - - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - - switch (unit_type) { - case UNITTYPE_CCX16: - printf("CCX-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_300: - printf(" HW-Ver 3.00-3.12\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)\n", feature_channels); -} - -int last_stage_init(void) -{ - print_fpga_info(); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - /* - * Neo hardware has no FPGA-DONE GPIO - */ - return 1; -} diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c deleted file mode 100644 index 9e1c57f..0000000 --- a/board/gdsys/405ex/405ex.c +++ /dev/null @@ -1,244 +0,0 @@ -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <asm/processor.h> -#include <asm/io.h> - -#include <gdsys_fpga.h> - -#include "405ex.h" - -#define REFLECTION_TESTPATTERN 0xdede -#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) - -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI -#define REFLECTION_TESTREG reflection_low -#else -#define REFLECTION_TESTREG reflection_high -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int get_fpga_state(unsigned dev) -{ - return gd->arch.fpga_state[dev]; -} - -int board_early_init_f(void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* - * Configure PFC (Pin Function Control) registers - */ - val = SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - return 0; -} - -int board_early_init_r(void) -{ - unsigned k; - unsigned ctr; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - /* - * reset FPGA - */ - gd405ex_init(); - - gd405ex_set_fpga_reset(1); - - gd405ex_setup_hw(); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ctr = 0; - while (!gd405ex_get_fpga_done(k)) { - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_DONE_FAILED; - break; - } - } - } - - udelay(10); - - gd405ex_set_fpga_reset(0); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - /* - * wait for fpga out of reset - */ - ctr = 0; - while (1) { - u16 val; - - FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - - FPGA_GET_REG(k, REFLECTION_TESTREG, &val); - if (val == REFLECTION_TESTPATTERN_INV) - break; - - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_REFLECTION_FAILED; - break; - } - } - } - - return 0; -} diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h deleted file mode 100644 index b15623f..0000000 --- a/board/gdsys/405ex/405ex.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __405EX_H_ -#define __405EX_H_ - -/* functions to be provided by board implementation */ -void gd405ex_init(void); -void gd405ex_set_fpga_reset(unsigned state); -void gd405ex_setup_hw(void); -int gd405ex_get_fpga_done(unsigned fpga); - -#endif /* __405EX_H_ */ diff --git a/board/gdsys/405ex/Kconfig b/board/gdsys/405ex/Kconfig deleted file mode 100644 index 52a8d89..0000000 --- a/board/gdsys/405ex/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IO64 - -config SYS_BOARD - default "405ex" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "io64" - -endif diff --git a/board/gdsys/405ex/MAINTAINERS b/board/gdsys/405ex/MAINTAINERS deleted file mode 100644 index 395b1ac..0000000 --- a/board/gdsys/405ex/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -405EX BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/405ex/ -F: include/configs/io64.h -F: configs/io64_defconfig diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile deleted file mode 100644 index a668460..0000000 --- a/board/gdsys/405ex/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := 405ex.o -obj-$(CONFIG_IO64) += io64.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c deleted file mode 100644 index 37e76c4..0000000 --- a/board/gdsys/405ex/chip_config.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c deleted file mode 100644 index 9ef965b..0000000 --- a/board/gdsys/405ex/io64.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * based on kilauea.c - * by Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/ppc4xx-gpio.h> -#include <flash.h> - -#include <pca9698.h> - -#include "405ex.h" -#include <gdsys_fpga.h> - -#include <miiphy.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define PHYREG_CONTROL 0 -#define PHYREG_PAGE_ADDRESS 22 -#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 -#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 -#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 -#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) - -enum { - UNITTYPE_CCD_SWITCH = 1, -}; - -enum { - HWVER_100 = 0, - HWVER_110 = 1, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -static inline void blank_string(int size) -{ - int i; - - for (i = 0; i < size; i++) - putc('\b'); - for (i = 0; i < size; i++) - putc(' '); - for (i = 0; i < size; i++) - putc('\b'); -} - -/* - * Board early initialization function - */ -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -static void print_fpga_info(unsigned dev) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - int fpga_state = get_fpga_state(dev); - - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - unsigned feature_expansion; - - FPGA_GET_REG(dev, versions, &versions); - FPGA_GET_REG(dev, fpga_version, &fpga_version); - FPGA_GET_REG(dev, fpga_features, &fpga_features); - - printf("FPGA%d: ", dev); - if (fpga_state & FPGA_STATE_PLATFORM) - printf("(legacy) "); - - if (fpga_state & FPGA_STATE_DONE_FAILED) { - printf(" done timed out\n"); - return; - } - - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { - printf(" refelectione test failed\n"); - return; - } - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - feature_expansion = fpga_features & (1<<15); - - switch (unit_type) { - case UNITTYPE_CCD_SWITCH: - printf("CCD-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)", feature_channels); - - printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: CATCenter Io64\n"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - return 0; -} - -int configure_gbit_phy(char *bus, unsigned char addr) -{ - unsigned short value; - - /* select page 0 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch to powerdown */ - if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - &value)) - goto err_out; - if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - value | 0x0004)) - goto err_out; - /* select page 2 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* disable SGMII autonegotiation */ - if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) - goto err_out; - /* select page 0 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch from powerdown to normal operation */ - if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - &value)) - goto err_out; - if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - value & ~0x0004)) - goto err_out; - /* reset phy so settings take effect */ - if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) - goto err_out; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -int verify_gbit_phy(char *bus, unsigned char addr) -{ - unsigned short value; - - /* select page 2 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* verify SGMII link status */ - if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) - goto err_out; - if (!(value & (1 << 10))) - return -2; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -int last_stage_init(void) -{ - unsigned int k; - unsigned int fpga; - int failed = 0; - char str_phys[] = "Setup PHYs -"; - char str_serdes[] = "Start SERDES blocks"; - char str_channels[] = "Start FPGA channels"; - char str_locks[] = "Verify SERDES locks"; - char str_hicb[] = "Verify HICB status"; - char str_status[] = "Verify PHY status -"; - char slash[] = "\\|/-\\|/-"; - - print_fpga_info(0); - print_fpga_info(1); - - /* setup Gbit PHYs */ - puts("TRANS: "); - puts(str_phys); - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) { - configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); - putc('\b'); - putc(slash[k % 8]); - } - - mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) { - configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); - putc('\b'); - putc(slash[k % 8]); - } - blank_string(strlen(str_phys)); - - /* take fpga serdes blocks out of reset */ - puts(str_serdes); - udelay(500000); - FPGA_SET_REG(0, quad_serdes_reset, 0); - FPGA_SET_REG(1, quad_serdes_reset, 0); - blank_string(strlen(str_serdes)); - - /* take channels out of reset */ - puts(str_channels); - udelay(500000); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) - FPGA_SET_REG(fpga, ch[k].config_int, 0); - } - blank_string(strlen(str_channels)); - - /* verify channels serdes lock */ - puts(str_locks); - udelay(500000); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) { - u16 status; - FPGA_GET_REG(fpga, ch[k].status_int, &status); - if (!(status & (1 << 4))) { - failed = 1; - printf("fpga %d channel %d: no serdes lock\n", - fpga, k); - } - /* reset events */ - FPGA_SET_REG(fpga, ch[k].status_int, 0); - } - } - blank_string(strlen(str_locks)); - - /* verify hicb_status */ - puts(str_hicb); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) { - u16 status; - FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status); - if (status) - printf("fpga %d hicb %d: hicb status %04x\n", - fpga, k, status); - /* reset events */ - FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); - } - } - blank_string(strlen(str_hicb)); - - /* verify phy status */ - puts(str_status); - for (k = 0; k < 32; ++k) { - if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { - printf("verify baseboard phy %d failed\n", k); - failed = 1; - } - putc('\b'); - putc(slash[k % 8]); - } - for (k = 0; k < 32; ++k) { - if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { - printf("verify extensionboard phy %d failed\n", k); - failed = 1; - } - putc('\b'); - putc(slash[k % 8]); - } - blank_string(strlen(str_status)); - - printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); - - return 0; -} - -void gd405ex_init(void) -{ - unsigned int k; - - if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; - } else { - pca9698_direction_output(0x22, 39, 1); - } -} - -void gd405ex_set_fpga_reset(unsigned state) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } - } else { - pca9698_set_value(0x22, 39, state ? 0 : 1); - } -} - -void gd405ex_setup_hw(void) -{ - gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); - gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); -} - -int gd405ex_get_fpga_done(unsigned fpga) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) - return in_le16((void *)LATCH3_BASE) - & CONFIG_SYS_FPGA_DONE(fpga); - else - return pca9698_get_value(0x22, fpga ? 9 : 8); -} diff --git a/board/gdsys/dlvision/Kconfig b/board/gdsys/dlvision/Kconfig deleted file mode 100644 index 8db4fbe..0000000 --- a/board/gdsys/dlvision/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DLVISION - -config SYS_BOARD - default "dlvision" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "dlvision" - -endif diff --git a/board/gdsys/dlvision/MAINTAINERS b/board/gdsys/dlvision/MAINTAINERS deleted file mode 100644 index e4d40f8..0000000 --- a/board/gdsys/dlvision/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DLVISION BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/dlvision/ -F: include/configs/dlvision.h -F: configs/dlvision_defconfig diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile deleted file mode 100644 index 755eb4c..0000000 --- a/board/gdsys/dlvision/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dlvision.o diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c deleted file mode 100644 index 32f7ba3..0000000 --- a/board/gdsys/dlvision/dlvision.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -enum { - HWTYPE_DLVISION_CPU = 0, - HWTYPE_DLVISION_CON = 1, -}; - -#define HWREV_100 6 - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * setup io-latches - */ - out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0); - out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002); - out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000); - return 0; -} - -int misc_init_r(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26); - u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36); - u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76); - u8 unit_type; - u8 local_con; - u8 audio; - u8 hardware_version; - - printf("Board: "); - - unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00; - local_con = (channel2_msr & 0x20) ? 0x01 : 0x00; - audio = (channel3_msr & 0x20) ? 0x01 : 0x00; - hardware_version = - ((channel7_msr & 0x20) ? 0x01 : 0x00) - | ((channel7_msr & 0x80) ? 0x02 : 0x00) - | ((channel7_msr & 0x40) ? 0x04 : 0x00); - - switch (unit_type) { - case HWTYPE_DLVISION_CON: - printf("DL-Vision-CON"); - break; - - case HWTYPE_DLVISION_CPU: - printf("DL-Vision-CPU"); - break; - - default: - printf("UnitType %d, unsupported", unit_type); - break; - } - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); - - switch (hardware_version) { - case HWREV_100: - printf("HW-Ver 1.00"); - break; - - default: - printf("HW-Ver %d, unsupported", - hardware_version); - break; - } - - if (local_con) - printf(", local console"); - - if (audio) - printf(", audio support"); - - puts("\n"); - - return 0; -} diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig deleted file mode 100644 index 1f21c89..0000000 --- a/board/gdsys/gdppc440etx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_GDPPC440ETX - -config SYS_BOARD - default "gdppc440etx" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "gdppc440etx" - -endif diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS deleted file mode 100644 index cd8d1c6..0000000 --- a/board/gdsys/gdppc440etx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GDPPC440ETX BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/gdppc440etx/ -F: include/configs/gdppc440etx.h -F: configs/gdppc440etx_defconfig diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile deleted file mode 100644 index 7e3fc38..0000000 --- a/board/gdsys/gdppc440etx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = gdppc440etx.o -extra-y += init.o diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk deleted file mode 100644 index 73341a5..0000000 --- a/board/gdsys/gdppc440etx/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# G&D 440EP/GR ETX-Module -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c deleted file mode 100644 index 04191df..0000000 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2008 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/yosemite/yosemite.c - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/4xx_pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* info for FLASH chips */ -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -int board_early_init_f(void) -{ - register uint reg; - - /* - * Setup the external bus controller/chip selects - */ - mfebc(EBC0_CFG, reg); - mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */ - - /* - * Setup the GPIO pins - */ - - /* setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); - - /* setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /* UART0 and UART1*/ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); - - /* disable boot-eeprom WP */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); - out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /* - * Setup other serial configuration - */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ - mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - return 0; -} - -int misc_init_r(void) -{ - uint pbcr; - int size_val; - uint sz; - - /* Re-do sizing to get full correct info */ - mfebc(PB0CR, pbcr); - - if (gd->bd->bi_flashsize > 0x08000000) - panic("Max. flash banksize is 128 MB!\n"); - - for (sz = gd->bd->bi_flashsize, size_val = 7; - ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) - sz <<= 1; - - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(PB0CR, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override weak pci_pre_init() - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - /* First call common code */ - __pci_pre_init(hose); - - /* enable 66 MHz ext. Clock */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); - out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S deleted file mode 100644 index 2db84b5..0000000 --- a/board/gdsys/gdppc440etx/init.S +++ /dev/null @@ -1,59 +0,0 @@ -/* -* (C) Copyright 2008 -* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de -* -* based on board/amcc/yosemite/init.S -* original Copyright not specified there - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> - -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use - * the speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, - 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G ) - - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, - 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, - 0, AC_RW | SA_IG ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, - 0, AC_RW | SA_IG ) - - tlbtab_end diff --git a/board/gdsys/intip/Kconfig b/board/gdsys/intip/Kconfig deleted file mode 100644 index 479bb12..0000000 --- a/board/gdsys/intip/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_INTIP - -config SYS_BOARD - default "intip" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "intip" - -endif diff --git a/board/gdsys/intip/MAINTAINERS b/board/gdsys/intip/MAINTAINERS deleted file mode 100644 index c99d507..0000000 --- a/board/gdsys/intip/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -INTIP BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/intip/ -F: include/configs/intip.h -F: configs/devconcenter_defconfig -F: configs/intip_defconfig diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile deleted file mode 100644 index 2fbc983..0000000 --- a/board/gdsys/intip/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := intip.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/gdsys/intip/chip_config.c b/board/gdsys/intip/chip_config.c deleted file mode 100644 index ea276a3..0000000 --- a/board/gdsys/intip/chip_config.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/intip/config.mk b/board/gdsys/intip/config.mk deleted file mode 100644 index c8c53e2..0000000 --- a/board/gdsys/intip/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2008-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# G&D CompactCenter -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S deleted file mode 100644 index 1fc2a2f..0000000 --- a/board/gdsys/intip/init.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/canyonlands/init.S - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) /* TLB 0 */ - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) -#endif - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, - AC_RW | SA_IG) - - /* TLB-entry for NVRAM */ - tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for UART */ - tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for IO */ - tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, - 4, AC_RWX | SA_IG) - - /* AHB: Internal USB Peripherals (USB, SATA) */ - tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, - AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c deleted file mode 100644 index 2d7d789..0000000 --- a/board/gdsys/intip/intip.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/canyonlands/canyonlands.c - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc440.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/4xx_pcie.h> -#include <asm/ppc4xx-gpio.h> - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -DECLARE_GLOBAL_DATA_PTR; - -#define CONFIG_SYS_BCSR3_PCIE 0x10 - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * enable GPIO 49-63 - * UART0: 4 pins - */ - mtsdr(SDR0_PFC0, 0x00007fff); - mtsdr(SDR0_PFC1, 0x00040000); - - /* Enable PCI host functionality in SDR0_PCI0 */ - mtsdr(SDR0_PCI0, 0xe0000000); - - mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - - /* Trigger board component reset */ - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); - udelay(50); - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf); - udelay(50); - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); - - return 0; -} - -int get_cpu_num(void) -{ - int cpu = NA_OR_UNKNOWN_CPU; - - return cpu; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - -#ifdef CONFIG_DEVCONCENTER - printf("Board: DevCon-Center"); -#else - printf("Board: Intip"); -#endif - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int board_early_init_r(void) -{ - /* - * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH - * (Spansion 29GL512), but the boot EBC mapping only supports a maximum - * of 16MBytes (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfn00.0000 -> 4.cn00.0000 - */ - - u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ? - EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB; - - /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L - | bxcr_bw - | EBC_BXCR_BU_RW - | EBC_BXCR_BW_16BIT); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - u32 eth_cfg; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - /* disable SGMII mode */ - eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII0_ENABLE); - /* Set the for 2 RGMII mode */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -extern void __ft_board_setup(void *blob, bd_t *bd); - -int ft_board_setup(void *blob, bd_t *bd) -{ - __ft_board_setup(blob, bd); - - fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", - "disabled", sizeof("disabled"), 1); - - fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", - "disabled", sizeof("disabled"), 1); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 1b8e035..86b257f 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -9,7 +9,6 @@ #include <command.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/ppc4xx-gpio.h> #include <asm/global_data.h> #include "mpc8308.h" |