powerpc: remove 4xx support

There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

8 files changed, 0 insertions, 1411 deletions

diff --git a/board/liebherr/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig
deleted file mode 100644
index ec8349d..0000000
--- a/board/liebherr/lwmon5/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LWMON5
-
-config SYS_BOARD
-	default "lwmon5"
-
-config SYS_VENDOR
-	default "liebherr"
-
-config SYS_CONFIG_NAME
-	default "lwmon5"
-
-endif
diff --git a/board/liebherr/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS
deleted file mode 100644
index df45730..0000000
--- a/board/liebherr/lwmon5/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LWMON5 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/liebherr/lwmon5/
-F:	include/configs/lwmon5.h
-F:	configs/lwmon5_defconfig
diff --git a/board/liebherr/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile
deleted file mode 100644
index 02478ca..0000000
--- a/board/liebherr/lwmon5/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= lwmon5.o kbd.o sdram.o
-extra-y	+= init.o
diff --git a/board/liebherr/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk
deleted file mode 100644
index d0348e8..0000000
--- a/board/liebherr/lwmon5/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/liebherr/lwmon5/init.S b/board/liebherr/lwmon5/init.S
deleted file mode 100644
index e5207c2..0000000
--- a/board/liebherr/lwmon5/init.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
-	/* TLB-entry for PCI Memory */
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
-	/* TLB-entry for the FPGA Chip select 2 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the FPGA Chip select 3 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the LIME Controller */
-	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for Internal Registers & OCM */
-	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I)
-
-	/*TLB-entry PCI registers*/
-	tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG)
-
-	/* TLB-entry for peripherals */
-	tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/liebherr/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c
deleted file mode 100644
index d6c0a20..0000000
--- a/board/liebherr/lwmon5/kbd.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <console.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h>	/* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define	_NOT_USED_	0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG	0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG	0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define	KEYBD_CMD_READ_KEYS	0x01
-#define KEYBD_CMD_READ_VERSION	0x02
-#define KEYBD_CMD_READ_STATUS	0x03
-#define KEYBD_CMD_RESET_ERRORS	0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK	0x3F
-#define	KEYBD_STATUS_H_RESET	0x20
-#define KEYBD_STATUS_BROWNOUT	0x10
-#define KEYBD_STATUS_WD_RESET	0x08
-#define KEYBD_STATUS_OVERLOAD	0x04
-#define KEYBD_STATUS_ILLEGAL_WR	0x02
-#define KEYBD_STATUS_ILLEGAL_RD	0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN	2	/* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define	KEYBD_DATALEN		6	/* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function:     int board_postclk_init (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    This function is the board_postclk_init() method implementation
-Z*               for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
-	kbd_init();
-
-	return (0);
-}
-
-static void kbd_init (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar tmp_data[KEYBD_DATALEN];
-	uchar val, errcd;
-	int i;
-
-	i2c_set_bus_num(0);
-
-	gd->arch.kbd_status = 0;
-
-	/* Forced by PIC. Delays <= 175us loose */
-	udelay(1000);
-
-	/* Read initial keyboard error code */
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &errcd, 1);
-	/* clear unused bits */
-	errcd &= KEYBD_STATUS_MASK;
-	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
-	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
-	if (errcd) {
-		gd->arch.kbd_status |= errcd << 8;
-	}
-	/* Reset error code and verify */
-	val = KEYBD_CMD_RESET_ERRORS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
-
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &val, 1);
-
-	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
-	if (val) {			/* permanent error, report it */
-		gd->arch.kbd_status |= val;
-		return;
-	}
-
-	/*
-	 * Read current keyboard state.
-	 *
-	 * After the error reset it may take some time before the
-	 * keyboard PIC picks up a valid keyboard scan - the total
-	 * scan time is approx. 1.6 ms (information by Martin Rajek,
-	 * 28 Sep 2002). We read a couple of times for the keyboard
-	 * to stabilize, using a big enough delay.
-	 * 10 times should be enough. If the data is still changing,
-	 * we use what we get :-(
-	 */
-
-	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
-	for (i=0; i<10; ++i) {
-		val = KEYBD_CMD_READ_KEYS;
-		i2c_write (kbd_addr, 0, 0, &val, 1);
-		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
-			/* consistent state, done */
-			break;
-		}
-		/* remeber last state, delay, and retry */
-		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
-		udelay (5000);
-	}
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
-	uchar buf[sizeof(*data)];
-	int rval;
-
-	if (i2c_read(dspic_addr, reg, 2, buf, 2))
-		return -1;
-
-	rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
-	*data = (buf[0] << 8) | buf[1];
-
-	return rval;
-}
-
-
-/***********************************************************************
-F* Function:     int misc_init_r (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned, even in the case of a keyboard
-P*                    error.
- *
-Z* Intention:    This function is the misc_init_r() method implementation
-Z*               for the lwmon board.
-Z*               The keyboard controller is initialized and the result
-Z*               of a read copied to the environment variable "keybd".
-Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z*               this key, and if found display to the LCD will be enabled.
-Z*               The keys in "keybd" are checked against the magic
-Z*               keycommands defined in the environment.
-Z*               See also key_match().
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar kbd_init_status = gd->arch.kbd_status >> 8;
-	uchar kbd_status = gd->arch.kbd_status;
-	uchar val;
-	ushort data, inv_data;
-	char *str;
-	int i;
-
-	if (kbd_init_status) {
-		printf ("KEYBD: Error %02X\n", kbd_init_status);
-	}
-	if (kbd_status) {		/* permanent error, report it */
-		printf ("*** Keyboard error code %02X ***\n", kbd_status);
-		sprintf (keybd_env, "%02X", kbd_status);
-		setenv ("keybd", keybd_env);
-		return 0;
-	}
-
-	/*
-	 * Now we know that we have a working  keyboard,  so  disable
-	 * all output to the LCD except when a key press is detected.
-	 */
-
-	if ((console_assign (stdout, "serial") < 0) ||
-		(console_assign (stderr, "serial") < 0)) {
-		printf ("Can't assign serial port as output device\n");
-	}
-
-	/* Read Version */
-	val = KEYBD_CMD_READ_VERSION;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
-	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
-	/* Read current keyboard state */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	/* read out start key from bse01 received via can */
-	_dspic_read(DSPIC_PON_STATUS_REG, &data);
-	/* check highbyte from status register */
-	if (data > 0xFF) {
-		_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
-		/* check inverse data */
-		if ((data+inv_data) == 0xFFFF) {
-			/* don't overwrite local key */
-			if (kbd_data[1] == 0) {
-				/* read key value */
-				_dspic_read(DSPIC_PON_KEY_REG, &data);
-				str = (char *)&data;
-				/* swap bytes */
-				kbd_data[1] = str[1];
-				kbd_data[2] = str[0];
-				printf("CAN received startkey: 0x%X\n", data);
-			}
-		}
-	}
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
-	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
-		if ((console_assign (stdout, "lcd") < 0) ||
-			(console_assign (stderr, "lcd") < 0)) {
-			printf ("Can't assign LCD display as output device\n");
-		}
-	}
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-#endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-	return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	uchar compare[KEYBD_DATALEN-1];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-/***********************************************************************
-F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters:   uchar *kbd_data
-P*                - The keys to match against our magic definitions
-P*
-P* Returnvalue:  uchar *
-P*                - != NULL: Pointer to the corresponding command(s)
-P*                     NULL: No magic is about to happen
- *
-Z* Intention:    Check if pressed key(s) match magic sequence,
-Z*               and return the command string associated with that key(s).
-Z*
-Z*               If no key press was decoded, NULL is returned.
-Z*
-Z*               Note: the first character of the argument will be
-Z*                     overwritten with the "magic charcter code" of the
-Z*                     decoded key(s), or '\0'.
-Z*
-Z*               Note: the string points to static environment data
-Z*                     and must be saved before you call any function that
-Z*                     modifies the environment.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-		debug ("### Check magic \"%s\"\n", magic);
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-			debug ("### Set PREBOOT to $(%s): \"%s\"\n",
-					cmd_name, cmd ? cmd : "<<NULL>>");
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-	debug ("### Delete PREBOOT\n");
-	*kbd_data = '\0';
-	return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F*                           int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters:   cmd_tbl_t *cmdtp
-P*                - Pointer to our command table entry
-P*               int flag
-P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
-P*                  a repetition
-P*               int argc
-P*                - Argument count
-P*               char * const argv[]
-P*                - Array of the actual arguments
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    Implement the "kbd" command.
-Z*               The keyboard status is read.  The result is printed on
-Z*               the console and written into the "keybd" environment
-Z*               variable.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar val;
-	int i;
-
-#if 0 /* Done in kbd_init */
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	kbd,	1,	1,	do_kbd,
-	"read keyboard status",
-	""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar val;
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
diff --git a/board/liebherr/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c
deleted file mode 100644
index bb99a3b..0000000
--- a/board/liebherr/lwmon5/lwmon5.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <video.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
-
-	/* PLB Write pipelining disabled. Denali Core workaround */
-	mtdcr(PLB4A0_ACR, 0xDE000000);
-	mtdcr(PLB4A1_ACR, 0xDE000000);
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
-	mtdcr(UIC0ER, 0x00000000);  /* disable all */
-	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
-	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
-	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC1ER, 0x00000000);  /* disable all */
-	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
-	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC2ER, 0x00000000);  /* disable all */
-	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
-	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-
-	/* Trace Pins are disabled. SDR0_PFC0 Register */
-	mtsdr(SDR0_PFC0, 0x0);
-
-	/* select Ethernet pins */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	/* SMII via ZMII */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
-		SDR0_PFC1_SELECT_CONFIG_6;
-	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
-		SDR0_PFC2_SELECT_CONFIG_6;
-
-	/* enable SPI (SCP) */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
-	mtsdr(SDR0_PFC2, sdr0_pfc2);
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-	mtsdr(SDR0_PFC4, 0x80000000);
-
-	/* PCI arbiter disabled */
-	/* PCI Host Configuration disbaled */
-	mfsdr(SDR0_PCI0, reg);
-	reg = 0;
-	mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
-	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-	/* enable the CAN transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
-	reg = 0; /* reuse as counter */
-	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
-			& ~CONFIG_SYS_DSPIC_TEST_MASK);
-	while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
-		udelay(1000);
-	}
-	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
-		/* set "boot error" flag */
-		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
-			CONFIG_SYS_DSPIC_TEST_MASK);
-	}
-#endif
-
-	/*
-	 * Reset PHY's:
-	 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
-	 * upon reset, and with the first reset upon powerup, the addresses are
-	 * not latched reliable, since the IRQ line is multiplexed with an
-	 * MDIO address. A 2nd reset at this time will make sure, that the
-	 * correct address is latched.
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
-	return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
-	return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
-	return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
-	u32 val0, val1;
-
-	/*
-	 * lwmon5 is manufactured in 2 different board versions:
-	 * The lwmon5a board has 64MiB NOR flash instead of the
-	 * 128MiB of the original lwmon5. Unfortunately the CFI driver
-	 * will report 2 banks of 64MiB even for the smaller flash
-	 * chip, since the bank is mirrored. To fix this, we bring
-	 * one bank into CFI query mode and read its response. This
-	 * enables us to detect the real number of flash devices/
-	 * banks which will be used later on by the common CFI driver.
-	 */
-
-	/* Put bank 0 into CFI command mode and read */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
-	val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
-	val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
-	/* Reset flash again out of query mode */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
-	/* When not identical, we have 2 different flash devices/banks */
-	if (val0 != val1)
-		return 0;
-
-	/*
-	 * Now we're sure that we're running on a LWMON5a board with
-	 * only 64MiB NOR flash in one bank:
-	 *
-	 * Set flash base address and bank count for CFI driver probing.
-	 */
-	cfi_flash_num_flash_banks = 1;
-	lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 pbcr;
-	int size_val = 0;
-	u32 reg;
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1, sdr0_srst;
-
-	/*
-	 * FLASH stuff...
-	 */
-
-	/* Re-do sizing to get full correct info */
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	mfebc(PB0CR, pbcr);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(PB0CR, pbcr);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size(gd->bd->bi_flashstart, 0);
-
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-	/* Env protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-	/*
-	 * USB suff...
-	 */
-
-	/* Reset USB */
-	/* Reset of USB2PHY0 must be active at least 10 us  */
-	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
-	udelay(2000);
-
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
-	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
-	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
-	udelay(2000);
-
-	/* Errata CHIP_6 */
-
-	/* 1. Set internal PHY configuration */
-	/* SDR Setting */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	mfsdr(SDR0_USB0, usb2d0cr);
-	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
-
-	/*
-	 * An 8-bit/60MHz interface is the only possible alternative
-	 * when connecting the Device to the PHY
-	 */
-	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
-	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
-
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-	mtsdr(SDR0_USB0, usb2d0cr);
-	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	/* 2. De-assert internal PHY reset */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-
-	/* 3. Wait for more than 1 ms */
-	udelay(2000);
-
-	/* 4. De-assert USB 2.0 Host main reset */
-	mfsdr(SDR0_SRST0, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
-	mtsdr(SDR0_SRST0, sdr0_srst);
-	udelay(1000);
-
-	/* 5. De-assert reset of OPB2 cores */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-	udelay(1000);
-
-	/* 6. Set EHCI Configure FLAG */
-
-	/* 7. Reassert internal PHY reset: */
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
-	udelay(1000);
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-	printf("USB:   Host(int phy) Device(ext phy)\n");
-
-	/*
-	 * Clear PLB4A0_ACR[WRP]
-	 * This fix will make the MAL burst disabling patch for the Linux
-	 * EMAC driver obsolete.
-	 */
-	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
-	mtdcr(PLB4A0_ACR, reg);
-
-	/*
-	 * Init matrix keyboard
-	 */
-	misc_init_r_kbd();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-void hw_watchdog_reset(void)
-{
-	int val;
-#if defined(CONFIG_WD_MAX_RATE)
-	unsigned long long ct = get_ticks();
-
-	/*
-	 * Don't allow watch-dog triggering more frequently than
-	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
-	 */
-	if (ct >= gd->arch.wdt_last) {
-		if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
-			return;
-	} else {
-		/* Time base counter had been reset */
-		if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
-		    CONFIG_WD_MAX_RATE)
-			return;
-	}
-	gd->arch.wdt_last = get_ticks();
-#endif
-
-	/*
-	 * Toggle watchdog output
-	 */
-	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
-	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if ((strcmp(argv[1], "on") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
-	else if ((strcmp(argv[1], "off") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
-	else
-		return cmd_usage(cmdtp);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	eepromwp,	2,	0,	do_eeprom_wp,
-	"eeprom write protect off/on",
-	"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
-	{ 0x0100, 0x00000f00 },
-	{ 0x0020, 0x801401df },
-	{ 0x0024, 0x00000000 },
-	{ 0x0028, 0x00000000 },
-	{ 0x002c, 0x00000000 },
-	{ 0x0110, 0x00000000 },
-	{ 0x0114, 0x00000000 },
-	{ 0x0118, 0x01df0280 },
-	{ 0x0004, 0x031f0000 },
-	{ 0x0008, 0x027f027f },
-	{ 0x000c, 0x015f028f },
-	{ 0x0010, 0x020c0000 },
-	{ 0x0014, 0x01df01ea },
-	{ 0x0018, 0x00000000 },
-	{ 0x001c, 0x01e00280 },
-	{ 0x0100, 0x80010f00 },
-	{ 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	mb862xx.winSizeX = 640;
-	mb862xx.winSizeY = 480;
-	mb862xx.gdfBytesPP = 2;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
-	return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS	0x64
-
-static void board_backlight_brightness(int brightness)
-{
-	if (brightness > 0) {
-		/* pwm duty, lamp on */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
-	} else {
-		/* lamp off */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
-	}
-}
-
-void board_backlight_switch(int flag)
-{
-	char * param;
-	int rc;
-
-	if (flag) {
-		param = getenv("brightness");
-		rc = param ? simple_strtol(param, NULL, 10) : -1;
-		if (rc < 0)
-			rc = DEFAULT_BRIGHTNESS;
-	} else {
-		rc = 0;
-	}
-	board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
-	else
-		info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
-	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (strcmp(s, "yes") == 0))
-		return 0;
-
-	return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	const gdc_regs *regs = board_get_regs();
-
-	/*
-	 * Setup PFC registers, mainly for ethernet support
-	 * later on in Linux
-	 */
-	board_early_init_f();
-
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
-	udelay(300);
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
-	while (regs->index) {
-		out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
-			 regs->index, regs->value);
-		regs++;
-	}
-
-	board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c
deleted file mode 100644
index 4a65d74..0000000
--- a/board/liebherr/lwmon5/sdram.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
-	u32 val;
-
-	mfsdram(DDR0_22, val);
-	val &= DDR0_22_CTRL_RAW_MASK;
-	if (val)
-		return 1;
-	else
-		return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
-	PPC4xx_SYS_INFO board_cfg;
-	u32 val;
-
-	if (is_ecc_enabled())
-		puts(" (ECC");
-	else
-		puts(" (ECC not");
-
-	get_sys_info(&board_cfg);
-	printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
-	mfsdram(DDR0_03, val);
-	val = DDR0_03_CASLAT_DECODE(val);
-	printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
-	/*
-	 * Controller idle status cannot be determined for Denali
-	 * DDR2 code. Just return here.
-	 */
-}
-
-static void program_ecc(u32 start_address,
-			u32 num_bytes,
-			u32 tlb_word2_i_value)
-{
-	u32 val;
-	u32 current_addr = start_address;
-	u32 size;
-	int bytes_remaining;
-
-	sync();
-	wait_ddr_idle();
-
-	/*
-	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
-	 * bytes of SDRAM.
-	 */
-	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
-	/*
-	 * We have to write the ECC bytes by zeroing and flushing in smaller
-	 * steps, since the whole 256MByte takes too long for the external
-	 * watchdog.
-	 */
-	while (bytes_remaining > 0) {
-		size = min((64 << 20), bytes_remaining);
-
-		/* Write zero's to SDRAM */
-		dcbz_area(current_addr, size);
-
-		/* Write modified dcache lines back to memory */
-		clean_dcache_range(current_addr, current_addr + size);
-
-		current_addr += 64 << 20;
-		bytes_remaining -= 64 << 20;
-		WATCHDOG_RESET();
-	}
-
-	sync();
-	wait_ddr_idle();
-
-	/* Clear error status */
-	mfsdram(DDR0_00, val);
-	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
-	/* Set 'int_mask' parameter to functionnal value */
-	mfsdram(DDR0_01, val);
-	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
-	sync();
-	wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * dram_init -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-int dram_init(void)
-{
-	/* CL=4 */
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
-	mtsdram(DDR0_04, 0x0B030300);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0003C812);
-	mtsdram(DDR0_07, 0x00090100);
-	mtsdram(DDR0_08, 0x03c80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_11, 0x000CC800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1e000000);
-	mtsdram(DDR0_18, 0x1e1e1e1e);
-	mtsdram(DDR0_19, 0x1e1e1e1e);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
-#else
-	mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
-	mtsdram(DDR0_23, 0x01000000);
-	mtsdram(DDR0_24, 0x01010001);
-
-	mtsdram(DDR0_26, 0x2D93028A);
-	mtsdram(DDR0_27, 0x0784682B);
-
-	mtsdram(DDR0_28, 0x00000080);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000008);
-
-	mtsdram(DDR0_43, 0x050A0200);
-	mtsdram(DDR0_44, 0x00000005);
-	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
-	denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
-	/* -----------------------------------------------------------+
-	 * Perform data eye search if requested.
-	 * ----------------------------------------------------------*/
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    TLB_WORD2_I_ENABLE);
-	denali_core_search_data_eye();
-	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
-	/*
-	 * Program tlb entries for this size (dynamic)
-	 */
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
-	/*
-	 * Setup 2nd TLB with same physical address but different virtual address
-	 * with cache enabled. This is done for fast ECC generation.
-	 */
-	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * Now after initialization (auto-calibration and ECC generation)
-	 * remove the TLB entries with caches enabled and program again with
-	 * desired cache functionality
-	 */
-	remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
-
-	return 0;
-}