diff options
| author | Stephen Warren <swarren@nvidia.com> | 2016-04-21 22:03:37 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-05-04 20:31:04 (GMT) |
| commit | bbca7108db79076d3a9a9c112792d7c4608a665c (patch) | |
| tree | b5e299fd7d6933fbf5ba43d726ea981341986f37 /board/nvidia | |
| parent | f5c6db84e71c60bfc7ae746bfb2cd1090d0b8765 (diff) | |
| download | u-boot-fsl-qoriq-bbca7108db79076d3a9a9c112792d7c4608a665c.tar.xz | |
ARM: tegra: import latest Jetson TK1 spreadsheet
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.
The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia')
| -rw-r--r-- | board/nvidia/jetson-tk1/jetson-tk1.c | 3 | ||||
| -rw-r--r-- | board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 12 |
2 files changed, 14 insertions, 1 deletions
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 14f0ce5..a66b710 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -31,6 +31,9 @@ void pinmux_init(void) pinmux_config_drvgrp_table(jetson_tk1_drvgrps, ARRAY_SIZE(jetson_tk1_drvgrps)); + + pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps, + ARRAY_SIZE(jetson_tk1_mipipadctrlgrps)); } #ifdef CONFIG_PCI_TEGRA diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index b2b2057..00e0cdc 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), }; @@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = { }; +#define MIPIPADCTRLCFG(_grp, _mux) \ + { \ + .grp = PMUX_MIPIPADCTRLGRP_##_grp, \ + .func = PMUX_FUNC_##_mux, \ + } + +static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = { + /* grp, mux */ + MIPIPADCTRLCFG(DSI_B, DSI_B), +}; + #endif /* PINMUX_CONFIG_JETSON_TK1_H */ |