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authorHaiying Wang <Haiying.Wang@freescale.com>2008-10-03 16:36:39 (GMT)
committerWolfgang Denk <wd@denx.de>2008-10-18 19:54:04 (GMT)
commitdbbbb3abeff325855cae76e33d69d5665631443f (patch)
tree2df59a7ac7364e4c501e228c74db3cd5f14ad3b1 /board/socrates
parent1c9aa76bf9013069e24258f46f4687c9f98a02d6 (diff)
downloadu-boot-fsl-qoriq-dbbbb3abeff325855cae76e33d69d5665631443f.tar.xz
Make DDR interleaving mode work correctly
Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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