diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2017-04-10 22:02:59 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 15:57:21 (GMT) |
| commit | 280057bd7dd623420b2d8b383fe5bbe26820bc93 (patch) | |
| tree | 14b79f1fdbb08d299ec1e434e359e73e17761e03 /board/st | |
| parent | d33a6a2f064a5dabfc277d5345aa03a9fbce4680 (diff) | |
| download | u-boot-fsl-qoriq-280057bd7dd623420b2d8b383fe5bbe26820bc93.tar.xz | |
stm32f7: use stm32f7 gpio driver supporting driver model
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/st')
| -rw-r--r-- | board/st/stm32f746-disco/stm32f746-disco.c | 70 |
1 files changed, 3 insertions, 67 deletions
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 370db15..45a2c47 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -20,37 +20,12 @@ DECLARE_GLOBAL_DATA_PTR; -const struct stm32_gpio_ctl gpio_ctl_gpout = { - .mode = STM32_GPIO_MODE_OUT, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_50M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF0 -}; - -static int fmc_setup_gpio(void) -{ - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); - clock_setup(GPIO_F_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); - clock_setup(GPIO_H_CLOCK_CFG); - - return 0; -} - int dram_init(void) { struct udevice *dev; struct ram_info ram; int rv; - rv = fmc_setup_gpio(); - if (rv) - return rv; - rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); @@ -73,37 +48,21 @@ int dram_init(void) return rv; } -int uart_setup_gpio(void) -{ - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_B_CLOCK_CFG); - return 0; -} - #ifdef CONFIG_ETH_DESIGNWARE - static int stmmac_setup(void) { clock_setup(SYSCFG_CLOCK_CFG); /* Set >RMII mode */ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; - - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); clock_setup(STMMAC_CLOCK_CFG); return 0; } -#endif -#ifdef CONFIG_STM32_QSPI - -static int qspi_setup(void) +int board_early_init_f(void) { - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); + stmmac_setup(); + return 0; } #endif @@ -113,29 +72,6 @@ u32 get_board_rev(void) return 0; } -int board_early_init_f(void) -{ - int res; - - res = uart_setup_gpio(); - if (res) - return res; - -#ifdef CONFIG_ETH_DESIGNWARE - res = stmmac_setup(); - if (res) - return res; -#endif - -#ifdef CONFIG_STM32_QSPI - res = qspi_setup(); - if (res) - return res; -#endif - - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |