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author | Wolfgang Denk <wd@pollux.denx.de> | 2006-07-19 15:52:30 (GMT) |
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committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-07-19 15:52:30 (GMT) |
commit | 45a212c4d73452beac30d4e405a9657b07d7edb3 (patch) | |
tree | 0308e0aac55b64e673310eb41d2750b467034833 /board/tqm5200/tqm5200.c | |
parent | bd3143f040ab186f8b665b3ada35840e3fc491e9 (diff) | |
download | u-boot-fsl-qoriq-45a212c4d73452beac30d4e405a9657b07d7edb3.tar.xz |
Add support for new TQM5200 revisions
- Support for TQM5200S (short version without graphic controller)
- Support for modules with 'N' type S29GL128N Spansion flashes
(requires changes to flash layout)
- Support for MPC5200B cpu (mostly support for second SDRAM bank)
Diffstat (limited to 'board/tqm5200/tqm5200.c')
-rw-r--r-- | board/tqm5200/tqm5200.c | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index c6309e3..1756e7f 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -1,11 +1,11 @@ /* - * (C) Copyright 2003-2004 + * (C) Copyright 2003-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * - * (C) Copyright 2004-2005 + * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * * See file CREDITS for list of people who contributed to this @@ -30,6 +30,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> #ifdef CONFIG_VIDEO_SM501 #include <sm501.h> @@ -101,6 +102,8 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; + #ifndef CFG_RAMBOOT ulong test1, test2; @@ -190,11 +193,31 @@ long int initdram (int board_type) } else { dramsize2 = 0; } - #endif /* CFG_RAMBOOT */ -/* return dramsize + dramsize2; */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + +#if defined(CONFIG_TQM5200_B) + return dramsize + dramsize2; +#else return dramsize; +#endif /* CONFIG_TQM5200_B */ } #elif defined(CONFIG_MGT5100) @@ -255,7 +278,11 @@ int checkboard (void) return 0; #endif #if defined (CONFIG_TQM5200) +#if defined(CONFIG_TQM5200_B) + puts ("Board: TQM5200 or TQM5200S (TQ-Components GmbH)\n"); +#else puts ("Board: TQM5200 (TQ-Components GmbH)\n"); +#endif /* CONFIG_TQM5200_B */ #endif #if defined (CONFIG_STK52XX) puts (" on a STK52XX baseboard\n"); |