Merge git://git.denx.de/u-boot-x86

22 files changed, 28 insertions, 79 deletions

diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
index f6f3748..fac562a 100644
--- a/board/advantech/som-db5800-som-6867/Kconfig
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_MACRONIX
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
index 5bed2c1..6158795 100644
--- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -17,8 +17,3 @@ int board_early_init_f(void)
 
 	return 0;
 }
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
index 24b8f69..c2649d2 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
index 7a5b765..1283eeb 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -28,11 +28,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
 int board_late_init(void)
 {
 	struct udevice *dev;
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 3ff64f4..cfa1d50 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -12,6 +12,17 @@ config SYS_SOC
 config SYS_TEXT_BASE
 	default 0x01110000
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	imply SPI_FLASH_ATMEL
+	imply SPI_FLASH_EON
+	imply SPI_FLASH_GIGADEVICE
+	imply SPI_FLASH_MACRONIX
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_STMICRO
+	imply SPI_FLASH_SST
+	imply SPI_FLASH_WINBOND
+
 comment "coreboot-specific options"
 
 config SYS_CONFIG_NAME
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
index 27ebe78..4f2ac89 100644
--- a/board/coreboot/coreboot/Makefile
+++ b/board/coreboot/coreboot/Makefile
@@ -12,4 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= coreboot_start.o coreboot.o
+obj-y	+= coreboot_start.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
deleted file mode 100644
index bb7f778..0000000
--- a/board/coreboot/coreboot/coreboot.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2013 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <cros_ec.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
index fca8b53..81a2575 100644
--- a/board/dfi/dfi-bt700/Kconfig
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c
index 1fbe36a..2adc202 100644
--- a/board/efi/efi-x86/efi.c
+++ b/board/efi/efi-x86/efi.c
@@ -5,9 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 8999b58..944716d 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 42615e1..dc22592 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,19 +5,3 @@
  */
 
 #include <common.h>
-#include <cros_ec.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index f2b9481..afbfe53 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_BROADWELL
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
index 3c3f5d4..5b5eb19 100644
--- a/board/google/chromebook_samus/samus.c
+++ b/board/google/chromebook_samus/samus.c
@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/cpu.h>
-
-int arch_early_init_r(void)
-{
-	return cpu_run_reference_code();
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index 2af3aa9..875df9d 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config SYS_CAR_ADDR
 	hex
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index e3baf88..2adc202 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig
index 597228f..a622499 100644
--- a/board/intel/bayleybay/Kconfig
+++ b/board/intel/bayleybay/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
index 95a617b..ed76448 100644
--- a/board/intel/cougarcanyon2/Kconfig
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -21,5 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_FSP
 	select BOARD_ROMSIZE_KB_2048
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_WINBOND
 
 endif
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index b30701a..1eed227 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -20,5 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUEENSBAY
 	select BOARD_ROMSIZE_KB_1024
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_SST
 
 endif
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 87a0ec4..1416c89 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
+	select SPI_FLASH_WINBOND
 
 config SMBIOS_PRODUCT_NAME
 	default "GalileoGen2"
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index 568bd4d..2fe1923 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -9,11 +9,6 @@
 #include <asm/arch/device.h>
 #include <asm/arch/quark.h>
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 /*
  * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
  *
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
index 7e975f9..a8668e4 100644
--- a/board/intel/minnowmax/Kconfig
+++ b/board/intel/minnowmax/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 99aed53..5bdb2fd 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -12,11 +12,6 @@
 
 #define GPIO_BANKE_NAME		"gpioe"
 
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	struct udevice *dev;