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| author | Wolfgang Denk <wd@denx.de> | 2007-12-27 01:01:15 (GMT) |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-12-27 01:01:15 (GMT) |
| commit | 0dcfe3a225a9436fc514f374a19242c672f1172b (patch) | |
| tree | 7ac3f382538d8919e475c6eaed25abb1af71e005 /board | |
| parent | 61fb15c516fef5631e305f1976d7b3a679725856 (diff) | |
| parent | 33ed73bc0e38d0f2b5c183d4629d8f207e5b9994 (diff) | |
| download | u-boot-fsl-qoriq-0dcfe3a225a9436fc514f374a19242c672f1172b.tar.xz | |
Merge branch 'master' of /home/wd/git/u-boot/custodians
Diffstat (limited to 'board')
| -rw-r--r-- | board/tqm8xx/flash.c | 4 | ||||
| -rw-r--r-- | board/tqm8xx/tqm8xx.c | 15 |
2 files changed, 12 insertions, 7 deletions
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c index db0a7e5..4342ebc 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqm8xx/flash.c @@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */ + #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ && !defined(CONFIG_TQM885D) # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ @@ -828,3 +830,5 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /*----------------------------------------------------------------------- */ + +#endif /* !defined(CFG_FLASH_CFI_DRIVER) */ diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index cebdcc0..fcd941e 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int); #define _NOT_USED_ 0xFFFFFFFF +/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ const uint sdram_table[] = { /* @@ -63,14 +64,14 @@ const uint sdram_table[] = /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, + 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* @@ -83,7 +84,7 @@ const uint sdram_table[] = /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ + 0xFFFFFC07, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, }; @@ -183,7 +184,7 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && - (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_br3 = CFG_BR3_PRELIM; } @@ -259,7 +260,7 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && - (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ /* * Check Bank 1 Memory Size * use current column settings |