Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h

Signed-off-by: Tom Rini <trini@konsulko.com>

28 files changed, 1173 insertions, 207 deletions

diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
index 20750fb..91e96ab 100644
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ b/board/advantech/dms-ba16/dms-ba16.c
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8033 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+	mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -303,7 +304,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
@@ -534,11 +536,61 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif
 
+void pmic_init(void)
+{
+
+#define DA9063_ADDR 0x58
+#define BCORE2_CONF 0x9D
+#define BCORE1_CONF 0x9E
+#define BPRO_CONF 0x9F
+#define BIO_CONF 0xA0
+#define BMEM_CONF 0xA1
+#define BPERI_CONF 0xA2
+#define MODE_BIT_H 7
+#define MODE_BIT_L 6
+
+        uchar val;
+        i2c_set_bus_num(2);
+
+        i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
+
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
 	/*
 	 * We need at least 200ms between power on and backlight on
 	 * as per specifications from CHI MEI
@@ -555,11 +607,15 @@ int board_late_init(void)
 	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 
 	pwm_enable(0);
+#endif
 
 #ifdef CONFIG_CMD_SATA
 	setup_ba16_sata();
 #endif
 
+        /* board specific pmic init */
+        pmic_init();
+
 	return 0;
 }
 
diff --git a/board/denx/m28evk/Kconfig b/board/aries/m28evk/Kconfig
index dd4dc4d..ab5577c 100644
--- a/board/denx/m28evk/Kconfig
+++ b/board/aries/m28evk/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
 	default "m28evk"
 
 config SYS_VENDOR
-	default "denx"
+	default "aries"
 
 config SYS_SOC
 	default "mxs"
diff --git a/board/denx/m28evk/MAINTAINERS b/board/aries/m28evk/MAINTAINERS
index b0535a9..f600e7d 100644
--- a/board/denx/m28evk/MAINTAINERS
+++ b/board/aries/m28evk/MAINTAINERS
@@ -1,6 +1,6 @@
 M28EVK BOARD
 M:	Marek Vasut <marek.vasut@gmail.com>
 S:	Maintained
-F:	board/denx/m28evk/
+F:	board/aries/m28evk/
 F:	include/configs/m28evk.h
 F:	configs/m28evk_defconfig
diff --git a/board/denx/m28evk/Makefile b/board/aries/m28evk/Makefile
index 5e890b1..5e890b1 100644
--- a/board/denx/m28evk/Makefile
+++ b/board/aries/m28evk/Makefile
diff --git a/board/denx/m28evk/README b/board/aries/m28evk/README
index cb3ae20..9f0d995 100644
--- a/board/denx/m28evk/README
+++ b/board/aries/m28evk/README
@@ -1,12 +1,12 @@
-DENX M28EVK
-===========
+Aries M28EVK
+============
 
 Files of the M28/M28EVK port
 ----------------------------
 
 arch/arm/cpu/arm926ejs/mxs/	- The CPU support code for the Freescale i.MX28
 arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
-board/denx/m28evk/		- M28EVK board specific files
+board/aries/m28evk/		- M28EVK board specific files
 include/configs/m28evk.h	- M28EVK configuration file
 
 Follow the instructions from doc/README.mxs to generate a bootable SD card or to
diff --git a/board/denx/m28evk/m28evk.c b/board/aries/m28evk/m28evk.c
index 33d38cf..c990ea9 100644
--- a/board/denx/m28evk/m28evk.c
+++ b/board/aries/m28evk/m28evk.c
@@ -1,5 +1,5 @@
 /*
- * DENX M28 module
+ * Aries M28 module
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -93,7 +93,7 @@ int board_mmc_init(bd_t *bis)
 
 int fecmxc_mii_postcall(int phy)
 {
-#if	defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
+#if	defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10)
 	/* KZ8031 PHY on old boards. */
 	const uint32_t freq = 0x0080;
 #else
@@ -123,7 +123,7 @@ int board_eth_init(bd_t *bis)
 		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
 		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
 
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
 	/* Reset the new PHY */
 	gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
 	udelay(10000);
diff --git a/board/denx/m28evk/spl_boot.c b/board/aries/m28evk/spl_boot.c
index 5a1010e..e27a74e 100644
--- a/board/denx/m28evk/spl_boot.c
+++ b/board/aries/m28evk/spl_boot.c
@@ -1,5 +1,5 @@
 /*
- * DENX M28 Boot setup
+ * ARIES M28 Boot setup
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -56,7 +56,7 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
 
 	/* UART1 */
-#ifdef	CONFIG_DENX_M28_V10
+#ifdef	CONFIG_ARIES_M28_V10
 	MX28_PAD_AUART0_CTS__DUART_RX,
 	MX28_PAD_AUART0_RTS__DUART_TX,
 #else
@@ -132,7 +132,7 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
 	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
 #endif
 
diff --git a/board/denx/m53evk/Kconfig b/board/aries/m53evk/Kconfig
index 0696ad7..2d49b40 100644
--- a/board/denx/m53evk/Kconfig
+++ b/board/aries/m53evk/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
 	default "m53evk"
 
 config SYS_VENDOR
-	default "denx"
+	default "aries"
 
 config SYS_SOC
 	default "mx5"
diff --git a/board/denx/m53evk/MAINTAINERS b/board/aries/m53evk/MAINTAINERS
index 5d8c764..71137f0 100644
--- a/board/denx/m53evk/MAINTAINERS
+++ b/board/aries/m53evk/MAINTAINERS
@@ -1,6 +1,6 @@
 M53EVK BOARD
 M:	Marek Vasut <marek.vasut@gmail.com>
 S:	Maintained
-F:	board/denx/m53evk/
+F:	board/aries/m53evk/
 F:	include/configs/m53evk.h
 F:	configs/m53evk_defconfig
diff --git a/board/denx/m53evk/Makefile b/board/aries/m53evk/Makefile
index 19b8977..daa0fe4 100644
--- a/board/denx/m53evk/Makefile
+++ b/board/aries/m53evk/Makefile
@@ -1,5 +1,5 @@
 #
-# DENX M53EVK
+# Aries M53EVK
 # Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
 #
 # SPDX-License-Identifier:	GPL-2.0+
diff --git a/board/denx/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg
index c0e2602..ec855c8 100644
--- a/board/denx/m53evk/imximage.cfg
+++ b/board/aries/m53evk/imximage.cfg
@@ -1,5 +1,5 @@
 /*
- * DENX M53 DRAM init values
+ * Aries M53 DRAM init values
  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
diff --git a/board/denx/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c
index 1e4db24..14c60fc 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/aries/m53evk/m53evk.c
@@ -1,5 +1,5 @@
 /*
- * DENX M53 module
+ * Aries M53 module
  *
  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
  *
@@ -381,7 +381,7 @@ int board_init(void)
 
 int checkboard(void)
 {
-	puts("Board: DENX M53EVK\n");
+	puts("Board: Aries M53EVK\n");
 
 	return 0;
 }
diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README
index 5814b9d..bc0c0d0 100644
--- a/board/freescale/mx6sabresd/README
+++ b/board/freescale/mx6sabresd/README
@@ -1,17 +1,19 @@
 How to use and build U-Boot on mx6sabresd:
 ----------------------------------
 
-Currently there are three methods for booting mx6sabresd boards:
+Currently there are four methods for booting mx6sabresd boards:
 
-1. Booting via Normal U-Boot (u-boot.imx)
+1. Booting from SD card via normal U-Boot (u-boot.imx)
 
-2. Booting via SPL (SPL and u-boot.img)
+2. Booting from eMMC via normal U-Boot
 
-3. Booting via Falcon mode (SPL launches the kernel directly)
+3. Booting via SPL (SPL and u-boot.img)
 
+4. Booting via Falcon mode (SPL launches the kernel directly)
 
-1. Booting via Normal U-Boot
-----------------------------
+
+1. Booting from SD card via normal U-Boot
+-----------------------------------------
 
 $ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
 
@@ -28,7 +30,44 @@ This will generate the image called u-boot.imx.
 $ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
 
 
-2. Booting via SPL
+2. Booting from eMMC via normal U-Boot
+--------------------------------------
+
+$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
+
+or
+
+$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
+
+$ make
+
+This will generate the image called u-boot.imx.
+
+- Flash the u-boot.imx binary into the eMMC:
+
+Set SW6 to download mode: 00001100
+
+Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader
+tool (https://github.com/boundarydevices/imx_usb_loader):
+
+$ sudo ./imx_usb u-boot.imx
+
+In U-boot change the eMMC partition config:
+
+=> mmc partconf 2 1 0 0
+
+Mount the eMMC in the host PC:
+
+=> ums 0 mmc 2
+
+Flash the u-boot.imx binary
+
+$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync
+
+Set SW6 to eMMC 8-bit boot: 11010110
+
+
+3. Booting via SPL
 ------------------
 
 Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
@@ -48,7 +87,7 @@ $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
 $ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
 
 
-3. Booting via Falcon mode
+4. Booting via Falcon mode
 --------------------------
 
 $ make mx6sabresd_spl_defconfig
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 96c0e8c..d495433 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -47,11 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
-		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
@@ -155,157 +150,55 @@ static void setup_iomux_fec(void)
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* Power up LAN8720 PHY */
+	gpio_request(ETH_PHY_POWER, "eth_pwr");
 	gpio_direction_output(ETH_PHY_POWER , 1);
 	udelay(15000);
 }
 
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC1_BASE_ADDR},
-	{USDHC2_BASE_ADDR, 0, 4},
-	{USDHC3_BASE_ADDR, 0, 4},
-};
-
 int board_mmc_get_env_dev(int devno)
 {
 	return devno;
 }
 
-int board_mmc_getcd(struct mmc *mmc)
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
 
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
 
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
-	int i, ret;
-
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    USDHC1
-	 * mmc1                    USDHC2
-	 * mmc2                    USDHC3
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_direction_input(USDHC3_CD_GPIO);
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret) {
-			printf("Warning: failed to initialize "
-				"mmc dev %d\n", i);
-			return ret;
-		}
-	}
+	if (ret != 0)
+		return ret;
 
-	return 0;
-#else
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-	u32 val;
-	u32 port;
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 
-	val = readl(&src_regs->sbmr1);
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 
-	/* Boot from USDHC */
-	port = (val >> 11) & 0x3;
-	switch (port) {
-	case 0:
-		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
-						 ARRAY_SIZE(usdhc1_pads));
-		gpio_direction_input(USDHC1_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-		break;
-	case 1:
-		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
-						 ARRAY_SIZE(usdhc2_pads));
-		gpio_direction_input(USDHC2_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-		usdhc_cfg[0].max_bus_width = 4;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-		break;
-	case 2:
-		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
-						 ARRAY_SIZE(usdhc3_pads));
-		gpio_direction_input(USDHC3_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-		usdhc_cfg[0].max_bus_width = 4;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-		break;
-	}
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 
-	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
+	/* set SW1C staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
 
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-struct i2c_pads_info i2c_pad_info1 = {
-	.sda = {
-		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
-		.gp = IMX_GPIO_NR(3, 13),
-	},
-	.scl = {
-		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
-		.gp = IMX_GPIO_NR(3, 12),
-	},
-};
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 
-int power_init_board(void)
-{
-	struct pmic *p;
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
-		return -ENODEV;
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 
-	return pfuze_mode_init(p, APS_PFM);
+	return 0;
 }
 #endif
 
@@ -374,9 +267,7 @@ int board_ehci_hcd_init(int port)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#ifdef CONFIG_MXC_SPI
-	setup_spi();
-#endif
+
 	return 0;
 }
 
@@ -385,8 +276,9 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#ifdef CONFIG_MXC_SPI
+	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
+	setup_spi();
 #endif
 
 #ifdef	CONFIG_FEC_MXC
@@ -411,6 +303,76 @@ int checkboard(void)
 #include <spl.h>
 #include <libfdt.h>
 
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+	u32 port;
+
+	val = readl(&src_regs->sbmr1);
+
+	/* Boot from USDHC */
+	port = (val >> 11) & 0x3;
+	switch (port) {
+	case 0:
+		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+						 ARRAY_SIZE(usdhc1_pads));
+		gpio_direction_input(USDHC1_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		break;
+	case 1:
+		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+						 ARRAY_SIZE(usdhc2_pads));
+		gpio_direction_input(USDHC2_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		break;
+	case 2:
+		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+						 ARRAY_SIZE(usdhc3_pads));
+		gpio_direction_input(USDHC3_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		break;
+	}
+
+	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_sdqs0 = 0x00003030,
 	.dram_sdqs1 = 0x00003030,
diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS
index b44fb4d..265ddac 100644
--- a/board/gateworks/gw_ventana/MAINTAINERS
+++ b/board/gateworks/gw_ventana/MAINTAINERS
@@ -3,4 +3,6 @@ M:	Tim Harvey <tharvey@gateworks.com>
 S:	Maintained
 F:	board/gateworks/gw_ventana/
 F:	include/configs/gw_ventana.h
-F:	configs/gwventana_defconfig
+F:	configs/gwventana_nand_defconfig
+F:	configs/gwventana_emmc_defconfig
+F:	configs/gwventana_gw5904_defconfig
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 3dc5f88..56a7b3e 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -38,6 +38,44 @@ void setup_iomux_uart(void)
 }
 
 /* MMC */
+static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 4-bit microSD on SD2 */
+static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* CD */
+	IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 8-bit eMMC on SD2/NAND */
+static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -352,6 +390,107 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
 	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 };
 
+static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* VID_EN */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* 12V0_PWR_EN */
+	IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
+	/* BKLT_12VEN */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* EMMY_PDN# */
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
+	/* USBH1_PEN (EHCI) */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* USBDPC_PEN */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* TOUCH_RST */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+	/* AUDIO_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+	/* UART1_TEN# */
+	IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* LVDS_BKLEN # */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* RGMII_PDWN# */
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
+	/* TOUCH_IRQ# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* TOUCH_RST# */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* UART_RS485 */
+	IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
+	/* UART_HALF */
+	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
+	/* SKT1_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
+	/* SKT1_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
+	/* SKT2_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
+	/* SKT2_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* M2_OFF# */
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+	/* M2_WDIS# */
+	IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+	/* M2_RST# */
+	IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
+};
+
 /* Digital I/O */
 struct dio_cfg gw51xx_dio[] = {
 	{
@@ -566,6 +705,111 @@ struct dio_cfg gw553x_dio[] = {
 	},
 };
 
+struct dio_cfg gw560x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5903_dio[] = {
+};
+
+struct dio_cfg gw5904_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
+		IMX_GPIO_NR(2, 0),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
+		IMX_GPIO_NR(2, 1),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
+		IMX_GPIO_NR(2, 2),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
+		IMX_GPIO_NR(2, 3),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
+		IMX_GPIO_NR(2, 4),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
+		IMX_GPIO_NR(2, 5),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
+		IMX_GPIO_NR(2, 6),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
+		IMX_GPIO_NR(2, 7),
+		{ 0, 0 },
+		0
+	},
+};
+
 /*
  * Board Specific GPIO
  */
@@ -588,6 +832,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.dioi2c_en = IMX_GPIO_NR(4,  5),
 		.pcie_sson = IMX_GPIO_NR(1, 20),
 		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW51xx */
@@ -631,6 +876,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.rs232_en = GP_RS232_EN,
 		.otgpwr_en = IMX_GPIO_NR(3, 22),
 		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW53xx */
@@ -654,6 +900,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.rs232_en = GP_RS232_EN,
 		.otgpwr_en = IMX_GPIO_NR(3, 22),
 		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW54xx */
@@ -679,6 +926,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.rs232_en = GP_RS232_EN,
 		.otgpwr_en = IMX_GPIO_NR(3, 22),
 		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW551x */
@@ -726,6 +974,58 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.wdis = IMX_GPIO_NR(7, 12),
 		.otgpwr_en = IMX_GPIO_NR(3, 22),
 		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW560x */
+	{
+		.gpio_pads = gw560x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
+		.dio_cfg = gw560x_dio,
+		.dio_num = ARRAY_SIZE(gw560x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(4, 31),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.rs232_en = GP_RS232_EN,
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.otgpwr_en = IMX_GPIO_NR(4, 15),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW5903 */
+	{
+		.gpio_pads = gw5903_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
+		.dio_cfg = gw5903_dio,
+		.dio_num = ARRAY_SIZE(gw5903_dio),
+		.leds = {
+			IMX_GPIO_NR(6, 14),
+		},
+		.otgpwr_en = IMX_GPIO_NR(4, 15),
+		.mmc_cd = IMX_GPIO_NR(6, 11),
+	},
+
+	/* GW5904 */
+	{
+		.gpio_pads = gw5904_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
+		.dio_cfg = gw5904_dio,
+		.dio_num = ARRAY_SIZE(gw5904_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
 	},
 };
 
@@ -834,6 +1134,50 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 		gpio_direction_input(gpio_cfg[board].vsel_pin);
 		gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
 	}
+
+	/* microSD CD */
+	if (gpio_cfg[board].mmc_cd) {
+		gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
+		gpio_direction_input(gpio_cfg[board].mmc_cd);
+	}
+
+	/* Anything else board specific */
+	switch(board) {
+	case GW560x:
+		gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
+		gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
+		break;
+	case GW5903:
+		gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
+		gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+		gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
+		gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
+		gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
+		gpio_direction_input(IMX_GPIO_NR(4, 6));
+		gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
+		gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
+		gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
+		gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
+		break;
+	case GW5904:
+		gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
+		gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
+		gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
+		gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
+		gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
+		gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
+		gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
+		gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
+		break;
+	}
 }
 
 /* setup GPIO pinmux and default configuration per baseboard and env */
@@ -926,6 +1270,8 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 void setup_pmic(void)
 {
 	struct pmic *p;
+	struct ventana_board_info ventana_info;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 	u32 reg;
 
 	i2c_set_bus_num(CONFIG_I2C_PMIC);
@@ -958,23 +1304,40 @@ void setup_pmic(void)
 		debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
 		power_ltc3676_init(CONFIG_I2C_PMIC);
 		p = pmic_get("LTC3676_PMIC");
-		if (p && !pmic_probe(p)) {
-			puts("PMIC:  LTC3676\n");
-			/*
-			 * set board-specific scalar for max CPU frequency
-			 * per CPU based on the LDO enabled Operating Ranges
-			 * defined in the respective IMX6DQ and IMX6SDL
-			 * datasheets. The voltage resulting from the R1/R2
-			 * feedback inputs on Ventana is 1308mV. Note that this
-			 * is a bit shy of the Vmin of 1350mV in the datasheet
-			 * for LDO enabled mode but is as high as we can go.
-			 *
-			 * We will rely on an OS kernel driver to properly
-			 * regulate these per CPU operating point and use LDO
-			 * bypass mode when using the higher frequency
-			 * operating points to compensate as LDO bypass mode
-			 * allows the rails be 125mV lower.
-			 */
+		if (!p || pmic_probe(p))
+			return;
+		puts("PMIC:  LTC3676\n");
+		/*
+		 * set board-specific scalar for max CPU frequency
+		 * per CPU based on the LDO enabled Operating Ranges
+		 * defined in the respective IMX6DQ and IMX6SDL
+		 * datasheets. The voltage resulting from the R1/R2
+		 * feedback inputs on Ventana is 1308mV. Note that this
+		 * is a bit shy of the Vmin of 1350mV in the datasheet
+		 * for LDO enabled mode but is as high as we can go.
+		 */
+		switch (board) {
+		case GW560x:
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+			break;
+		case GW5903:
+			/* mask PGOOD during SW1 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+
+			/* mask PGOOD during SW4 transition */
+			pmic_reg_write(p, LTC3676_DVB4B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW4 (VDD_SOC) */
+			pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
+			break;
+		default:
 			/* mask PGOOD during SW1 transition */
 			pmic_reg_write(p, LTC3676_DVB1B,
 				       0x1f | LTC3676_PGOOD_MASK);
@@ -991,23 +1354,96 @@ void setup_pmic(void)
 }
 
 #ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+static struct fsl_esdhc_cfg usdhc_cfg[2];
 
 int board_mmc_init(bd_t *bis)
 {
-	/* Only one USDHC controller on Ventana */
-	SETUP_IOMUX_PADS(usdhc3_pads);
-	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg.max_bus_width = 4;
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+	struct ventana_board_info ventana_info;
+	int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int ret;
+
+	switch (board_type) {
+	case GW52xx:
+	case GW53xx:
+	case GW54xx:
+	case GW553x:
+		/* usdhc3: 4bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	case GW560x:
+		/* usdhc2: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc3: 4-bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5903:
+		/* usdhc3: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc2: 4-bit microSD */
+		SETUP_IOMUX_PADS(gw5904_mmc_pads);
+		usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5904:
+		/* usdhc3: 8bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	default:
+		/* doesn't have MMC */
+		return -1;
+	}
 }
 
 int board_mmc_getcd(struct mmc *mmc)
 {
+	struct ventana_board_info ventana_info;
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int gpio = gpio_cfg[board].mmc_cd;
+
 	/* Card Detect */
-	gpio_request(GP_SD3_CD, "sd_cd");
-	gpio_direction_input(GP_SD3_CD);
-	return !gpio_get_value(GP_SD3_CD);
+	switch (board) {
+	case GW560x:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+			return 1;
+		break;
+	case GW5903:
+	case GW5904:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+			return 1;
+		break;
+	}
+
+	if (gpio) {
+		debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
+		return !gpio_get_value(gpio);
+	}
+
+	return -1;
 }
+
 #endif /* CONFIG_FSL_ESDHC */
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 18909a0..3eb4c59 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -13,7 +13,6 @@
 
 /* GPIO's common to all baseboards */
 #define GP_PHY_RST	IMX_GPIO_NR(1, 30)
-#define GP_SD3_CD	IMX_GPIO_NR(7, 0)
 #define GP_RS232_EN	IMX_GPIO_NR(2, 11)
 #define GP_MSATA_SEL	IMX_GPIO_NR(2, 8)
 
@@ -79,6 +78,7 @@ struct ventana {
 	int rs232_en;
 	int otgpwr_en;
 	int vsel_pin;
+	int mmc_cd;
 	/* various features */
 	bool usd_vsel;
 };
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index 1382e5d..2c07a84 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -64,6 +64,7 @@ read_eeprom(int bus, struct ventana_board_info *info)
 	if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
 		baseboard = '0';
 
+	type = GW_UNKNOWN;
 	switch (baseboard) {
 	case '0': /* original GW5400-A prototype */
 		type = GW54proto;
@@ -91,10 +92,16 @@ read_eeprom(int bus, struct ventana_board_info *info)
 			type = GW553x;
 			break;
 		}
-		/* fall through */
-	default:
-		printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
-		type = GW_UNKNOWN;
+		break;
+	case '6':
+		if (info->model[4] == '0')
+			type = GW560x;
+		break;
+	case '9':
+		if (info->model[4] == '0' && info->model[5] == '3')
+			type = GW5903;
+		if (info->model[4] == '0' && info->model[5] == '4')
+			type = GW5904;
 		break;
 	}
 	return type;
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 613a275..68b1ddb 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -137,6 +137,10 @@ int gsc_info(int verbose)
 		break;
 	case '5': /* GW55xx */
 		break;
+	case '6': /* GW560x */
+		read_hwmon("VDD_IO4",  GSC_HWMON_VDD_IO4, 3);
+		read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
+		break;
 	}
 	return 0;
 }
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 3f9d2f7..dc8cd88 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -132,8 +132,9 @@ static void setup_iomux_enet(int gpio)
 	/* toggle PHY_RST# */
 	gpio_request(gpio, "phy_rst#");
 	gpio_direction_output(gpio, 0);
-	mdelay(2);
+	mdelay(10);
 	gpio_set_value(gpio, 1);
+	mdelay(100);
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
@@ -226,12 +227,56 @@ int board_phy_config(struct phy_device *phydev)
 		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 	}
 
+	/* TI DP83867 */
+	else if (phydev->phy_id == 0x2000a231) {
+		/* configure register 0x170 for ref CLKOUT */
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
+		val &= ~0x1f00;
+		val |= 0x0b00; /* chD tx clock*/
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+	}
+
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
 
 	return 0;
 }
 
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	/* GPIO[0] output, CLK125 */
+	debug("enabling RGMII_REFCLK\n");
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
+
+	/* RGMII delay - Physical Control register bit[15:14] */
+	debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
+	/* forced 1000mbps full-duplex link */
+	bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
+	phydev->autoneg = AUTONEG_DISABLE;
+	phydev->speed = SPEED_1000;
+	phydev->duplex = DUPLEX_FULL;
+
+	/* LED configuration: 7:4-green (8=Activity)  3:0 amber (9=10Link) */
+	bus->write(bus, 0x10, 0, 0x16, 0x8089);
+	bus->write(bus, 0x11, 0, 0x16, 0x8089);
+	bus->write(bus, 0x12, 0, 0x16, 0x8089);
+	bus->write(bus, 0x13, 0, 0x16, 0x8089);
+
+	return 0;
+}
+#endif // CONFIG_MV88E61XX_SWITCH
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FEC_MXC
@@ -661,6 +706,8 @@ int checkboard(void)
 static const struct boot_mode board_boot_modes[] = {
 	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
+	{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
 	{ NULL, 0 },
 };
 #endif
@@ -712,7 +759,8 @@ int misc_init_r(void)
 			setenv("fdt_file1", fdt);
 			if (board_type != GW551x &&
 			    board_type != GW552x &&
-			    board_type != GW553x)
+			    board_type != GW553x &&
+			    board_type != GW560x)
 				str[4] = 'x';
 			str[5] = 'x';
 			str[6] = 0;
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 8cc2a57..6060b44 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -374,6 +374,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
 	.p1_mpwrdlctl = 0x383A3930,
 };
 
+static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001F003F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F004E,
+	.p1_mpwldectrl1 = 0x0059001F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x42220225,
+	.p0_mpdgctrl1   = 0x0213021F,
+	.p1_mpdgctrl0   = 0x022C0242,
+	.p1_mpdgctrl1   = 0x022C0244,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x474A4C4A,
+	.p1_mprddlctl   = 0x48494C45,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3F3F3F36,
+	.p1_mpwrdlctl   = 0x3F36363F,
+};
+
 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 	/* write leveling calibration determine */
 	.p0_mpwldectrl0 = 0x002A0025,
@@ -510,10 +529,25 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 			calib = &mx6sdl_256x64_mmdc_calib;
 		debug("4gB density\n");
 	} else if (width == 64 && size_mb == 4096) {
-		mem = &mt41k512m16ha_125;
-		if (is_cpu_type(MXC_CPU_MX6Q))
-			calib = &mx6dq_512x64_mmdc_calib;
-		debug("8gB density\n");
+		switch(board_model) {
+		case GW5903:
+			/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
+			mem = &mt41k256m16ha_125;
+			debug("4gB density\n");
+			if (!is_cpu_type(MXC_CPU_MX6Q)) {
+				calib = &mx6sdl_256x64x2_mmdc_calib;
+				sysinfo.ncs = 2;
+				sysinfo.cs_density = 18; /* CS0_END=71 */
+				sysinfo.cs1_mirror = 1; /* mirror enabled */
+			}
+			break;
+		default:
+			mem = &mt41k512m16ha_125;
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				calib = &mx6dq_512x64_mmdc_calib;
+			debug("8gB density\n");
+			break;
+		}
 	}
 
 	if (!(mem && calib)) {
@@ -608,6 +642,20 @@ void board_init_f(ulong dummy)
 	memset(__bss_start, 0, __bss_end - __bss_start);
 }
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_NAND:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		spl_boot_list[2] = BOOT_DEVICE_UART;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	}
+}
+
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 /* its our chance to print info about boot device */
 void spl_board_init(void)
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index 9ffad58..8a42d67 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -112,6 +112,9 @@ enum {
 	GW551x,
 	GW552x,
 	GW553x,
+	GW560x,
+	GW5903,
+	GW5904,
 	GW_UNKNOWN,
 	GW_BADCRC,
 };
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
new file mode 100644
index 0000000..f5e2f58
--- /dev/null
+++ b/board/logicpd/imx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6LOGICPD
+
+config SYS_BOARD
+       default "imx6"
+
+config SYS_VENDOR
+       default "logicpd"
+
+config SYS_CONFIG_NAME
+       default "imx6_logic"
+
+endif
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
new file mode 100644
index 0000000..5db7d2c
--- /dev/null
+++ b/board/logicpd/imx6/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6LOGICPD BOARD
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/logicpd/imx6/
+F:     include/configs/imx6_logic.h
+F:     configs/imx6q_logic_defconfig
diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
new file mode 100644
index 0000000..337df92
--- /dev/null
+++ b/board/logicpd/imx6/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := imx6logic.o
+
diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
new file mode 100644
index 0000000..df43b55
--- /dev/null
+++ b/board/logicpd/imx6/README
@@ -0,0 +1,37 @@
+U-Boot for LogicPD i.MX6 Development Kit
+----------------------------------------
+
+This file contains information for the port of U-Boot to the Logic PD Development kit.
+
+Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
+board.  SOM has a built-in microSD socket, DDR and NAND flash.  The development kit has
+an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
+
+On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
+
+For more details about Logic PD i.MX6 Development kit, visit:
+https://www.logicpd.com/
+
+Building U-Boot for Logic PD Development Kit
+--------------------------------------------
+To build U-Boot for the Dual and Quad variants:
+
+ make imx6q_logic_defconfig
+ make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
+
+
+Flashing U-Boot into the SD card
+--------------------------------
+
+See README.imximage for details on booting from SD
+
+Flashing U-Boot into NAND
+-------------------------
+Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
+with:
+
+  kobs-ng init -v -x u-boot-dtb.imx
+
+Additional Support Documentation can be found at:
+https://support.logicpd.com/
+
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
new file mode 100644
index 0000000..5576799
--- /dev/null
+++ b/board/logicpd/imx6/imx6logic.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Author: Adam Ford <aford173@gmail.com>
+ *
+ * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
+ * and updates by Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void fixup_enet_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct gpio_desc nint;
+	struct gpio_desc reset;
+	int ret;
+
+	/* Set Ref Clock to 50 MHz */
+	enable_fec_anatop_clock(0, ENET_50MHZ);
+
+	/* Set GPIO_16 as ENET_REF_CLK_OUT */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	/* Request GPIO Pins to reset Ethernet with new clock */
+	ret = dm_gpio_lookup_name("GPIO4_7", &nint);
+	if (ret) {
+		printf("Unable to lookup GPIO4_7\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&nint, "eth0_nInt");
+	if (ret) {
+		printf("Unable to request eth0_nInt\n");
+		return;
+	}
+
+	/* Ensure nINT is input or PHY won't startup */
+	dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
+
+	ret = dm_gpio_lookup_name("GPIO4_9", &reset);
+	if (ret) {
+		printf("Unable to lookup GPIO4_9\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&reset, "eth0_reset");
+	if (ret) {
+		printf("Unable to request eth0_reset\n");
+		return;
+	}
+
+	/* Reset LAN8710A PHY */
+	dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
+	dm_gpio_set_value(&reset, 0);
+	udelay(150);
+	dm_gpio_set_value(&reset, 1);
+	mdelay(50);
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+static void setup_nand_pins(void)
+{
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	fixup_enet_clock();
+	setup_iomux_uart();
+	setup_nand_pins();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("board_name", "imx6logic");
+
+	if (is_mx6dq()) {
+		setenv("board_rev", "MX6DQ");
+		setenv("fdt_file", "imx6q-logicpd.dtb");
+	}
+
+	return 0;
+}
diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
new file mode 100644
index 0000000..b206548
--- /dev/null
+++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ * Adam Ford <aford173@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch-mx6/mx6-ddr.h"
+#include "asm/arch-mx6/iomux.h"
+#include "asm/arch-mx6/crm_regs.h"
+
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300
+DATA 4, CCM_CCGR5, 0x0F0000F3
+DATA 4, CCM_CCGR6, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 MX6_IOMUXC_GPR6 0x007F007F
+DATA 4 MX6_IOMUXC_GPR7 0x007F007F