* Patch by Stefan Roese, 06 Apr 2005:

  Updates for OCOTEA board:
  - Changed U-Boot size from 512kByte to 256kByte
  - Fixed flash driver to support boot from soldered user flash
  - Added README for switch from PIBS firmware to U-Boot

3 files changed, 79 insertions, 14 deletions

diff --git a/board/ocotea/config.mk b/board/ocotea/config.mk
index a71dbac..5543a4e 100644
--- a/board/ocotea/config.mk
+++ b/board/ocotea/config.mk
@@ -30,7 +30,7 @@
 ifeq ($(ramsym),1)
 TEXT_BASE = 0x07FD0000
 else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/ocotea/flash.c b/board/ocotea/flash.c
index f44984a..bc0d2c9 100644
--- a/board/ocotea/flash.c
+++ b/board/ocotea/flash.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
@@ -43,7 +43,9 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     BOOT_SMALL_FLASH        0x40 /* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
 #define     FLASH_ONBD_N            2	/* 00000010 */
 #define     FLASH_SRAM_SEL          1	/* 00000001 */
 
@@ -55,8 +57,8 @@
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
-	{0xFF800000, 0xFF900000, 0xFFC00000},	/* 0:000: configuraton 4 */
-	{0xFF900000, 0xFF800000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
 	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
@@ -131,6 +133,12 @@ unsigned long flash_init(void)
 		total_b += flash_info[i].size;
 	}
 
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[2]);
+
 	return total_b;
 }
 
@@ -153,6 +161,9 @@ void flash_print_info(flash_info_t * info)
 	case FLASH_MAN_AMD:
 		printf("AMD ");
 		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
 	case FLASH_MAN_FUJ:
 		printf("FUJITSU ");
 		break;
@@ -300,6 +311,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
+	case (FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
 	case (FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
@@ -312,8 +328,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040) ||
-	    (info->flash_id == FLASH_AMD016)) {
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	} else {
@@ -343,6 +359,15 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+		}
+
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
@@ -432,7 +457,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-			printf("Erasing sector %p\n", addr2);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
diff --git a/board/ocotea/ocotea.c b/board/ocotea/ocotea.c
index b4b5622..1c532a3 100644
--- a/board/ocotea/ocotea.c
+++ b/board/ocotea/ocotea.c
@@ -37,6 +37,15 @@ void fpga_init (void);
 int board_early_init_f (void)
 {
 	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
@@ -47,17 +56,49 @@ int board_early_init_f (void)
 	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
 
 	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
 	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
-	      EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 
 	/*-------------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -75,15 +116,15 @@ int board_early_init_f (void)
 	/*-------------------------------------------------------------------------+
 	  | 4 MB FLASH. Initialize bank 2 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
-	      EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 
 	/*-------------------------------------------------------------------------+
 	  | FPGA. Initialize bank 7 with default values.