Merge git://git.denx.de/u-boot-fsl-qoriq

8 files changed, 55 insertions, 53 deletions

diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index 1c2287d..0c3a54c 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -10,15 +10,15 @@
 #include <asm/arch/ns_access.h>
 #include <asm/arch/fsl_serdes.h>
 
-void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
+void set_devices_ns_access(unsigned long index, u16 val)
 {
 	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
 	u32 *reg;
 	uint32_t tmp;
 
-	reg = base + ns_dev->ind / 2;
+	reg = base + index / 2;
 	tmp = in_be32(reg);
-	if (ns_dev->ind % 2 == 0) {
+	if (index % 2 == 0) {
 		tmp &= 0x0000ffff;
 		tmp |= val << 16;
 	} else {
@@ -34,7 +34,7 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
 	int i;
 
 	for (i = 0; i < num; i++)
-		set_devices_ns_access(ns_dev + i, ns_dev[i].val);
+		set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
 }
 
 void enable_layerscape_ns_access(void)
@@ -50,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val)
 	switch (pcie) {
 #ifdef CONFIG_PCIE1
 	case PCIE1:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE1, val);
+		set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
 		return;
 #endif
 #ifdef CONFIG_PCIE2
 	case PCIE2:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE2, val);
+		set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
 		return;
 #endif
 #ifdef CONFIG_PCIE3
 	case PCIE3:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE3, val);
+		set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
 		return;
 #endif
 	default:
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 3340e4d..5854e2d 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -201,10 +201,6 @@ int board_init(void)
 
 	ls102xa_smmu_stream_id_init();
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 	return 0;
 }
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index ff32d5c..2da0677 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -435,7 +435,6 @@ void board_init_f(ulong dummy)
 	/* Allow OCRAM access permission as R/W */
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
-	enable_layerscape_ns_access();
 #endif
 
 	/*
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 057a11d..883abf7 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -261,10 +261,6 @@ int board_init(void)
 	config_serdes_mux();
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
 
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 1dd5e69..33f1afd 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -69,10 +69,6 @@ int board_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_SECURE_BOOT
 	/*
 	 * In case of Secure Boot, the IBR configures the SMMU
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
index 6a5076e..ccedf87 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e000000 00000000 00000000
+0c150012 0e000000 00000000 00000000
 11335559 40000012 60040000 c1000000
 00000000 00000000 00000000 00238800
 20124000 00003000 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
index d5265b8..d3b1522 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e000000 00000000 00000000
+0c150012 0e000000 00000000 00000000
 11335559 40005012 60040000 c1000000
 00000000 00000000 00000000 00238800
 20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index df2d768..d7122b3 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -204,25 +204,12 @@ int config_board_mux(int ctrl_type)
 
 int board_init(void)
 {
-	char *env_hwconfig;
-	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 #ifdef CONFIG_FSL_MC_ENET
 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 #endif
-	u32 val;
 
 	init_final_memctl_regs();
 
-	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
-
-	env_hwconfig = getenv("hwconfig");
-
-	if (hwconfig_f("dspi", env_hwconfig) &&
-	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
-		config_board_mux(MUX_TYPE_DSPI);
-	else
-		config_board_mux(MUX_TYPE_SDHC);
-
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
@@ -257,31 +244,31 @@ int board_early_init_f(void)
 
 int misc_init_r(void)
 {
-#ifdef CONFIG_FSL_QIXIS
-	/*
-	 * LS2081ARDB has smart voltage translator which needs
-	 * to be programmed as below
-	 */
-#ifndef CONFIG_TARGET_LS2081ARDB
-	u8 sw;
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = getenv("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
 
-	sw = QIXIS_READ(arch);
 	/*
-	 * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
+	 * LS2081ARDB RevF board has smart voltage translator
 	 * which needs to be programmed to enable high speed SD interface
 	 * by setting GPIO4_10 output to zero
 	 */
-	if ((sw & 0xf) == 0x5) {
-#endif
+#ifdef CONFIG_TARGET_LS2081ARDB
 		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 					    in_le32(GPIO4_GPDIR_ADDR)));
 		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 					    in_le32(GPIO4_GPDAT_ADDR)));
-#ifndef CONFIG_TARGET_LS2081ARDB
-	}
-#endif
 #endif
-
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
 
@@ -341,6 +328,32 @@ void board_quiesce_devices(void)
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
+void fsl_fdt_fixup_flash(void *fdt)
+{
+	int offset;
+
+/*
+ * IFC and QSPI are muxed on board.
+ * So disable IFC node in dts if QSPI is enabled or
+ * disable QSPI node in dts in case QSPI is not enabled.
+ */
+#ifdef CONFIG_FSL_QSPI
+	offset = fdt_path_offset(fdt, "/soc/ifc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/ifc");
+#else
+	offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/quadspi");
+#endif
+	if (offset < 0)
+		return;
+
+	fdt_status_disabled(fdt, offset);
+}
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	u64 base[CONFIG_NR_DRAM_BANKS];
@@ -368,6 +381,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fsl_fdt_fixup_dr_usb(blob, bd);
 
+	fsl_fdt_fixup_flash(blob);
+
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
 #endif