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| author | Tom Warren <twarren@nvidia.com> | 2013-04-03 21:39:30 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 18:01:38 (GMT) |
| commit | d94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e (patch) | |
| tree | 5bdef44cb41f3818fec6d5741654bba1348ef19a /board | |
| parent | b40f734af9fdc47a0993f1f94f32d40a86f30587 (diff) | |
| download | u-boot-fsl-qoriq-d94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e.tar.xz | |
Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions