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authorTom Rini <trini@konsulko.com>2017-08-04 11:23:32 (GMT)
committerTom Rini <trini@konsulko.com>2017-08-04 11:23:32 (GMT)
commitfe84c48eeb8e9cb0b8b80a4c0a53bb089adff9af (patch)
tree7b3d2b47abc9b9f11f0e79a591f590050912c68a /common
parent217324b23c4a73420633068efcdc396682894b1b (diff)
parentdf1cd46fb84922735e1c12f54b7202b0268dcddd (diff)
downloadu-boot-fsl-qoriq-fe84c48eeb8e9cb0b8b80a4c0a53bb089adff9af.tar.xz
Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2017.09 Zynq: - Add Z-Turn board support fpga: - Remove intermediate buffer from code Zynqmp: - dts cleanup - change psu_init handling - Add options to get silicon version - Fix time handling - Map OCM/TCM via MMU - Add new clock driver
Diffstat (limited to 'common')
-rw-r--r--common/board_f.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/common/board_f.c b/common/board_f.c
index 19b8055..5915e50 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -340,7 +340,7 @@ static int reserve_round_4k(void)
}
#ifdef CONFIG_ARM
-static int reserve_mmu(void)
+__weak int reserve_mmu(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */