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| author | Simon Glass <sjg@chromium.org> | 2016-11-13 21:22:16 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-11-26 00:59:32 (GMT) |
| commit | e70408c069795fc2084aaee65a1a6c5f42c91a8f (patch) | |
| tree | 022d813d71357c0c1cd6948dec459316924f90e6 /configs/chromebit_mickey_defconfig | |
| parent | 095e6c1f2dd65635543859ddf689e3d90ab6e5cd (diff) | |
| download | u-boot-fsl-qoriq-e70408c069795fc2084aaee65a1a6c5f42c91a8f.tar.xz | |
rockchip: Add support for veyron-mickey (Chromebit)
This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/chromebit_mickey_defconfig')
| -rw-r--r-- | configs/chromebit_mickey_defconfig | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig new file mode 100644 index 0000000..b118907 --- /dev/null +++ b/configs/chromebit_mickey_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_CHROMEBIT_MICKEY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DM_KEYBOARD=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_LIBFDT is not set |