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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 14:35:06 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 08:39:39 (GMT) |
| commit | 05b98ec3468547057666dd685b2a1615298c24cc (patch) | |
| tree | f6b4914a6cc6423e573dbf059ce8b8ae057f1659 /configs/galileo_defconfig | |
| parent | 5910955f3cf685c1ca4e4abd1546fc59da55239a (diff) | |
| download | u-boot-fsl-qoriq-05b98ec3468547057666dd685b2a1615298c24cc.tar.xz | |
x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/galileo_defconfig')
| -rw-r--r-- | configs/galileo_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index c0a937f..a3b564e 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -6,3 +6,4 @@ CONFIG_TARGET_GALILEO=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y CONFIG_ETH_DESIGNWARE=y +CONFIG_GENERATE_PIRQ_TABLE=y |