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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-12-03 15:08:19 (GMT) |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-12-20 00:32:41 (GMT) |
| commit | 181a3650113883728927928b3ac81ad6dade4b2c (patch) | |
| tree | 6f7f2589c4be06e1e746a0f23b3cc2e3e7e8b5a1 /cpu/mpc85xx/release.S | |
| parent | a5d212a263c58cc746481bf1fc878510533ce7d6 (diff) | |
| download | u-boot-fsl-qoriq-181a3650113883728927928b3ac81ad6dade4b2c.tar.xz | |
Set IVPR to kenrel entry point in second core boot page
Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'cpu/mpc85xx/release.S')
| -rw-r--r-- | cpu/mpc85xx/release.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 7c3e8a1..54c936c 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -157,6 +157,7 @@ __secondary_start_page: mfspr r0,SPRN_PIR stw r0,ENTRY_PIR(r10) + mtspr IVPR,r12 /* * Coming here, we know the cpu has one TLB mapping in TLB1[0] * which maps 0xfffff000-0xffffffff one-to-one. We set up a |