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authorKumar Gala <galak@kernel.crashing.org>2009-09-22 20:45:44 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 17:05:27 (GMT)
commit25bacf7a2b096496e2c58f2de4e5b2bce8fba038 (patch)
treea698d12a783a168d9285b5b18599d3fa7e717e9e /cpu/mpc85xx
parentcb0ff65c619efacdc0ba69aa8ee6ede7dd364a38 (diff)
downloadu-boot-fsl-qoriq-25bacf7a2b096496e2c58f2de4e5b2bce8fba038.tar.xz
ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/cpu_init.c4
-rw-r--r--cpu/mpc85xx/release.S3
2 files changed, 4 insertions, 3 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a6d1e99..a8d83b1 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -336,8 +336,8 @@ int cpu_init_r(void)
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
- mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
- while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+ mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
+ while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
;
/* enable the cache */
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 074b056..ecbd0d5 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -102,7 +102,8 @@ __secondary_start_page:
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync
- lis r3,L2CSR0_L2FI@h
+ lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+ ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
mtspr SPRN_L2CSR0,r3
1:
mfspr r3,SPRN_L2CSR0