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author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-10 19:54:55 (GMT) |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-16 02:30:08 (GMT) |
commit | 6d8565a1ed5acb01bad4a4cd74a93be5f7fb7f7c (patch) | |
tree | ddea3c52064b48f26d8d20f5034112ad94e65658 /cpu/mpc8xxx/ddr/ddr3_dimm_params.c | |
parent | 3e3c9c157b89eab2dc2f897899b1b95cd70c1a58 (diff) | |
download | u-boot-fsl-qoriq-6d8565a1ed5acb01bad4a4cd74a93be5f7fb7f7c.tar.xz |
ppc/8xxx: Misc DDR related fixes
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr/ddr3_dimm_params.c')
-rw-r--r-- | cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 13d234e..d4199ba 100644 --- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * calculate the organization and timing parameter @@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + nbit_primary_bus_width - nbit_sdram_width); - debug("DDR: DDR III rank density = 0x%08x\n", bsize); + debug("DDR: DDR III rank density = 0x%16lx\n", bsize); return bsize; } |